Displaying 20 results from an estimated 69 matches for "95054".
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5054
2016 Apr 21
12
[Bug 95054] New: KDE 5 / Plasma crashes with nouveau "fifo: gr engine fault on channel 2, recovering" or "gr: TRAP ch 2"
https://bugs.freedesktop.org/show_bug.cgi?id=95054
Bug ID: 95054
Summary: KDE 5 / Plasma crashes with nouveau "fifo: gr engine
fault on channel 2, recovering" or "gr: TRAP ch 2"
Product: xorg
Version: 7.4 (2008.09)
Hardware: x86-64 (AMD64)...
2008 Nov 18
3
[LLVMdev] 32 bit boolean results
Is there a way to tell LLVM to treat Boolean results as 32bit values
instead of 1 bit values?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 10
3
[LLVMdev] Determining the names of all the functions in a module
...determine how to extract the function name from either a
Function object
or a Module.
Any tips or ideas would be greatly appreciated.
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 23
2
[LLVMdev] Determining the register type of a MachineOperand
...e. i32, f32, etc..) I am
accessing from a MachineOperand? I.e. how do I get to the MVT struct, or
equivalent information, from a MachineOperand object?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 25
2
[LLVMdev] Going from argument to register and back
...rent set of assumptions,
but I would rather determine it dynamically so that I can change my
assumptions and still get the right results.
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 20
2
[LLVMdev] Virtual Register allocation across functions
...ons so that if I create a new virtual register in
a function that it doesn't use a virtual register allocated in any
previous function?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 24
2
[LLVMdev] SetCC tablegen pattern
...t all comparison results are always integers?
If I put GPRI32 as my destination register, it complains about register
classes not matching......
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Nov 18
0
[LLVMdev] 32 bit boolean results
...LLVM IR doesn't have a concept of C level booleans. What problem are
you trying to solve?
-Chris
>
> Thanks,
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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2008 Oct 14
3
[LLVMdev] CFG modifcations and code gen
...newExitPath->moveAfter(pHigh);
root->getParent()->RenumberBlocks();
So what am I doing wrong?
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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Name: mf...
2008 Sep 15
3
[LLVMdev] Bad legalization?
...@abs( i32 %x ) ; <i32>
[#uses=1]
store i32 %call, i32 addrspace(11)* %result
ret void
}
declare i32 @abs(...)
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 22
2
[LLVMdev] Register class conversions
....
So is it possible to have the register class I have setup for i32 type
be automatically converted to the generic register type instead of
aborting?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 17
2
[LLVMdev] store addrspace qualifier
...nd 3 is undef
So, how do I find out the address space? The reason being different
address spaces are accessed with different registers.
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 28
4
[LLVMdev] Using patterns inside patterns
Is there currently a way to use a pattern inside of another pattern?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 14
0
[LLVMdev] CFG modifcations and code gen
...);
> root->getParent()->RenumberBlocks();
>
> So what am I doing wrong?
>
> Thanks,
>
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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2008 Sep 22
1
[LLVMdev] Tablegen address space
Is there a known way to get pattern matching on the address space from
tablegen?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 23
1
[LLVMdev] Tablegen strings
...ead of just src0. Where
can I find the rules for the string pattern matcher so that I can added
arbitrary strings into my
definition.
Thanks,
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 24
0
[LLVMdev] Determining the register type of a MachineOperand
...g from a MachineOperand? I.e. how do I get to the MVT
> struct, or equivalent information, from a MachineOperand object?
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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2008 Oct 23
1
[LLVMdev] Tablegen and data type support
Is there a way for tablegen to generate patterns for all the data types
of a specific register class instead of just the first one?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Oct 28
1
[LLVMdev] Accessing InstrFormat.td fields
...= asmstr;
OpCodeModifier ocmod;
}
How do I set/read the ocmod struct from either SelectCode or a separate
phase? Is there an example of this?
Micah Villmow
Systems Engineer
Advanced Technology & Performance
Advanced Micro Devices Inc.
4555 Great America Pkwy,
Santa Clara, CA. 95054
P: 408-572-6219
F: 408-572-6596
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2008 Sep 11
0
[LLVMdev] Determining the names of all the functions in a module
...either
> a Function object
> or a Module.
>
> Any tips or ideas would be greatly appreciated.
>
> Thanks,
>
> Micah Villmow
> Systems Engineer
> Advanced Technology & Performance
> Advanced Micro Devices Inc.
> 4555 Great America Pkwy,
> Santa Clara, CA. 95054
> P: 408-572-6219
> F: 408-572-6596
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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