Displaying 4 results from an estimated 4 matches for "928r".
Did you mean:
928
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...reg31 R600_Reg128:%vreg6
register: %vreg31 +[896r,912r:0)
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31
register: %vreg32 +[912r,944r:0)
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
register: %vreg34 +[928r,960r:0)
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
register: %vreg35 +[944r,976r:0)
960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35 R600_Reg32:%vreg34
register: %vreg35 replace range with [944r,960r:1) RESULT: [944r,960r:1)[960r,976r:...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...r: %vreg31 +[896r,912r:0)
> 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>;
> R600_Reg128:%vreg32 R600_Reg32:%vreg31
> register: %vreg32 +[912r,944r:0)
> 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34
> R600_Reg128:%vreg6
> register: %vreg34 +[928r,960r:0)
> 944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
> register: %vreg35 +[944r,976r:0)
> 960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35
> R600_Reg32:%vreg34
> register: %vreg35 replace range with [944r,960r:1) RESULT...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2