Displaying 6 results from an estimated 6 matches for "8xi32".
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2018 Jul 24
2
KNL Vectorization with larger vector width
Hello,
I need help here. I am able to adjust the vector width through
WidestRegister value. When number of iterations=31 and I set vector
width=32 it gives <16xi32> and <8xi32> instructions.
However if i replicate same behavior with number of iterations=63 and I
set vector width=64, no vector instructions are emitted. it should do as
previous and gives <32xi32> and <16xi32> vector instructions.
How to do this?
What adjustments are needed?
Please help...
2018 Jul 24
2
KNL Vectorization with larger vector width
...65536;
here i changed 512 to 65536. Then in loopvectorize.cpp i did following;
assert(MaxVectorSize <= 2048 && "Did not expect to pack so many elements"
" into one vector!");
changed 64 to 2048.
It runs fine. I can see in IR <2048xi32> or <1024xi64> emission.
But I cannot see the vector mix like in default knl if iterations=15 we see
1<8xi32> and rest scalar. so here when i keep iteration=2047 i get all
scalar why is that so? similarly in polly as well i cant see vector mixes
like its happening for KNL it emits &...
2018 Mar 20
1
Polly -polly-prevect-width
i musing polly with vec-width=16 default my IR emits <16xi32> and remaining
as <4xi32> by using polly. I want my IR to emit <16xi32> and remaining left
as <8xi32>. How to do this?
i m trying to use -polly-prevect-width.
please help.
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2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function
2018 Jul 23
2
KNL Vectorization with larger vector width
...unable
to debug this. each time i debug it, it returns me vectorized IR in gdb.
My goal is simple when i mention my target name in opt it should vectorize
by keeping the vector width= highest supported by my target which is 2048.
So $ opt -O3 -mytarget 1.ll -o 1_opt.ll
1_opt.ll should emit <2048xi32>,
<1024xi32>.........................<32xi32> etc.
How to achieve this? Please help.
Thank You
Regards
On Fri, Jul 13, 2018 at 12:40 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 07/12/2018 02:32 PM, hameeza ahmed via llvm-dev wrote:
>
> Hello,
>
> If...
2008 Sep 30
4
[LLVMdev] Generalizing shuffle vector
...float4 f4a, f4b, f4c;
f4a = f8.hi;
f8.hi = f4b; f8.lo = f4c;
where hi and lo represent the high half and low half of the vector.
The outgoing IR is
%f4a = shufflevector <8xf32>%f8, undef, <4xi32> <0, 1, 2, 3>
%f8 = shufflevector <4xf32>%f4b, <4xf32>%f4c, <8xi32> <0, 1, 2, 3,
4, 5, 6, 7>
The problem with generating insert and extracts is that we can
generate poor code
%tmp16 = extractelement <4 x float> %f4b, i32 0
%f8a = insertelement <8 x float> %f8a, float %tmp16, i32 0
%tmp18 = extractelement <4 x fl...