search for: 8x32bits

...a single node and this may be fixed in the codegen. So I propose fixing it in one of the following ways: a) avoid doing "sext+and"=>"select" transformation for vectors longer than architectural register. b) fix select to avoid internal conversion 8x16bit (doing operations on 8x32bits is way more effective anyway). Dmitry. On Sat, Oct 26, 2013 at 4:25 AM, Nadav Rotem <nrotem at apple.com> wrote: > Hi Dmitry, > > Yes, this is a known problem with legalizing vector masks. The type <8 x > i1> is legalized to 8 x i16, on SSE, but your operands are legali...

Hi Dmitry, Yes, this is a known problem with legalizing vector masks. The type <8 x i1> is legalized to 8 x i16, on SSE, but your operands are legalized to <4 x i32>. Type-legalization is performed per-node and we don’t have a good way to support instructions that mix the mask and operand type. Why does ISPC generate illegal vector types ? Does ISPC rely on the LLVM codegen to

Nadav, The problem appears only for vectors longer than available hardware register (in doubleword elements, i.e. more than 4 on SSE4 and more than 8 on AVX). Select does weird thing. <8 x i1> mask comes as two XMM registers, select converts them to a single XMM registers (i.e. 8 x 16 bit), immediately after it converts back to two XMM registers and does blend. Conversion forth and back has