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https://bugs.freedesktop.org/show_bug.cgi?id=39495 Summary: MX440-8X TV-detect/framebuffer problem Product: xorg Version: unspecified Platform: x86 (IA32) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists...

...x + 1980630 the part that strikes me as most odd is the bend between 2M and 2.5M. i haven''t read the ferret algorithm, but i would expect either linear or hyperbolic performance over time. however, the graph seems to indicate a particular breaking point after which performance is cut by 8x. is this behavior normal/expected? is there anything i could be doing to speed up an index of this size? (the index grows to ~12G while indexing, then gets shrunk to ~6G by the optimization) thanks for the help! -m --- MODEL CODE class MyModel < ActiveRecord::Base # think of body/title in...

Just wondering if anyone is using CentOS 4.2 with a LSI MRSATA300-8X controller? I just got a new SuperMicro server with this controller, and the install works just fine, but it panics when booting after install. For all I know (yet), it might be a problem with the server itself, but I suspect it's the LSI controller that's the problem. I've just sta...

...e_cancel+0x76) [0x7f3e7fd8b4b6] -> /usr/lib/dovecot/modules/lib01_acl_plugin.so(+0xe1b2) [0x7f3e7f2691b2] -> /usr/lib/dovecot/libdovecot-storage.so.0(+0x45913) [0x7f3e7fd8b913] -> /usr/lib/dovecot/libdovecot-storage.so.0(mailbox_move+0x29) [0x7f3e7fd8bb29] -> dovecot/imap [yyy at xxx.de 8x.1xx.1x.xx8 UID MOVE](+0xf955) [0x562ff2225955] -> dovecot/imap [yyy at xxx.de 8x.1xx.1x.xx8 UID MOVE](command_exec+0xa6) [0x562ff2232296] -> dovecot/imap [yyy at xxx.de 8x.1xx.1x.xx8 UID MOVE](+0x1a602) [0x562ff2230602] -> dovecot/imap [yyy at xxx.de 8x.1xx.1x.xx8 UID MOVE](+0x1a690) [0x56...

...PT part. name _______ : '", gpt_part->lba_first, gpt_part->lba_last, gpt_part->attribs); for (i = 0; i < sizeof(gpt_part->name); i++) { @@ -559,11 +560,11 @@ void disk_gpt_header_dump(const struct disk_gpt_header *const gpt) "GPT header size ______ : 0x%.8x\n" "GPT header checksum __ : 0x%.8x\n" "GPT reserved _________ : '%4.4s'\n" - "GPT LBA current ______ : 0x%.16llx\n" - "GPT LBA alternative __ : 0x%.16llx\n" - "GPT LBA first usable _ : 0x%.16llx\n" - "GPT LBA...

Hello, dovecot version 2.3.13 (89f716dc2) The dovecot solr installation guide [1] gives links and configuration info for sorl 7.7.0. However, sorl was deprecated some time ago. Those links to 7.7.0 don't work anymore. Sorl is currently available in versions 8.11.2 and 9.1.1 [3]. Specifically, one section in the guide states [2]: [[ Install schema.xml and solrconfig.xml Copy

...'m using ael language and I need to pick up a call from outside to an internal number. for example: i'm 120 the phone 100 rings, it's a call from outside. now I pick up the call with: *8100 and I would expect to answer the call but the response is Declined the Puckup code is below: _*8X! => { Pickup(${EXTEN:2}); Hangup(); } the problem is if an another number ( 130) calls the phone 120 and I pick up with *8100, this works! I respond to the caller 130. I tried this code below: _*8X! => { SET(GLOBAL(PICKUPMARK)=${EXTEN:2}); Pickup(${EXTEN:2}@PICKUPMARK); } but i...

...e damned slow mesa library...)? How can I link compiz to mesa's GL library? And will it go with this solution? I have the same problem also in a notebook with AIGLX and the videocard is a Mobility Radeon 9200 P.S.: I can't buy a new Geffo becouse my motherboard is not PCI-E and is not AGP 8x it only support AGP 4x...I have an old pc but it does everithing I want...I'm not a hard gamer. ByE all and thankU for the answers...i think that lot of U don't have so much sparetime 4 this questions...especially who works at Novell...or Suse...is Suse become a part of Novell?

...acters, the text output of meminfo.c32 gets to be back in line with versions prior to 6.03. --- a/syslinux-6.04-pre1/com32/modules/meminfo.c +++ b/syslinux-6.04-pre1/com32/modules/meminfo.c @@ -71,12 +71,12 @@ if (oreg.ecx.l >= 24) { /* ebx base length end type */ - printf("%8x %016" PRIx64 "x %016" PRIx64 "x %016" PRIx64 "x %d [%x]", + printf("%8x %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %d [%x]", ireg.ebx.l, ed.base, ed.len, ed.base + ed.len, ed.type, ed.extattr); } else {...

Hello Thank for adding mail_log plugin in Dovecot POP3/IMAP server. But when I am use "mail_log" in pop3 secction Dovecot getting the following log message: ... Jan 26 15:34:11 rtr dovecot: pop3-login: Login: user=<gk2>, method=PLAIN, rip=8x.xx.xx.xx, lip=8x.xx.xx.xxx Jan 26 15:34:11 rtr dovecot: POP3(gk2): dlopen(/opt/dovecot/v1.0rc19/lib/dovecot/pop3/lib20_mail_log_plugin.so) failed: /op t/dovecot/v1.0rc19/lib/dovecot/pop3/lib20_mail_log_plugin.so: undefined symbol: str_sanitize Jan 26 15:34:11 rtr dovecot: child 29501 (pop3) retu...

Hello to all, I''ve lucked onto a case of Opteron 850''s and hope to try some 4 way and 8 way systems with Xen. Can someone recommend a good 8x or even 4x socket 940 board that will be condusive to a good experience with Xen? This will be only for Paravirtualized guests (3.0.4). My hope is to play more with Xen''s credit scheduler and try some of the arch mixing possible in 3.0.4-testing. Thanks in advance for recommendations, es...

Hi ZFS Discuss, I have a 8x 1TB RAIDZ running on Samsung 1TB 5400rpm drives with 512b sectors. I will be replacing all of these with 8x Western Digital 2TB drives with support for 4K sectors. The replacement plan will be to swap out each of the 8 drives until all are replaced and the new size (~16TB) is available with a `zf...

I've seen this problem mentioned many times in the various FAQs and How-Tos on the Internet, but none of the solutions presented therein have worked for me. [global] workgroup = UNIX server string = OPTIMUS interfaces = eth0 log level = 1 log file = /var/log/samba/%m.log max log size = 0 # socket options = TCP_NODELAY

...llocators, it means that we will have one LiveIntervalUnion per atom instead of one per physical register as we do it today. > > That's one way to make an algorithm scale well--just make the best case expensive enough. Actually, I like this approach very much, I just wonder if we need to 8x liveintervals for pure 64-bit code. 8x is not necessary, atoms are not bytes or bits. The x86 integer registers would each map to two atoms, except for the 8-bit registers which map to a single atom. Today, we have live interval unions for %rax, %eax, %ax, %ah, and %al. Using atoms, we would onl...

...t in the lspci output below - the AGP card is on bus 0 and SiS card on bus 1 (AGP bus behind the AGP bridge). The SiS card is not used (can be disabled in BIOS but it does not improve things - as the AGP capability of the host bridge remains active). As seen in dmesg below, kernel tries to set AGP 8x mode for all AGP devices, including the AGP 4x TNT2 card which is not even connected to the AGP bridge. Setting nouveau.agpmode=0 makes it work but how can we make this case work automatically? Radeon driver does some "ring test" and if it fails, it disables AGP mode and retries. That s...

Hello list, I'm trying to use zaphfc, the module loads ok, and it identifies the hfc boards in the machine. The problem is: whenever i try to ztcfg -vv I get the following: 8x------------------- Zaptel Configuration ====================== SPAN 1: CCS/ AMI Build-out: 399-533 feet (DSX-1) Channel map: Channel 01: Individual Clear channel (Default) (Slaves: 01) Channel 02: Individual Clear channel (Default) (Slaves: 02) Channel 03: D-channel (Default) (Slaves: 03)...

...behave like that with my old NV11 card and this screen, a pair of years ago. Nvidia fixed it eventually. Interesting part of dmesg (not much to see there): [ 12.124804] agpgart: Found an AGP 3.5 compliant device at 0000:00:00.0. [ 12.124825] agpgart: Putting AGP V3 device at 0000:00:00.0 into 8x mode [ 12.124925] agpgart: Putting AGP V3 device at 0000:01:00.0 into 8x mode [ 1354.480303] [drm] Initialized drm 1.1.0 20060810 [ 1354.484501] [drm] Detected an NV40 generation card (0x047300a1) [ 1354.484507] [drm] Initialized nouveau 0.0.10 drm-2.3.0-1274-g6905c7a29d2a3bc0e on minor 0 [ 1356....

...nd basic allocators, it means that we will have one LiveIntervalUnion per atom instead of one per physical register as we do it today. That's one way to make an algorithm scale well--just make the best case expensive enough. Actually, I like this approach very much, I just wonder if we need to 8x liveintervals for pure 64-bit code. -Andy

...) : nulls(); #else @@ -244,22 +247,22 @@ static void DisassembleObject(const ObjectFile *Obj) { #endif for (Index = Start; Index < End; Index += Size) { MCInst Inst; - if (DisAsm->getInstruction(Inst, Size, memoryObject, Index, + outs() << format("%8x:\t", Index); + if (DisAsm->getInstruction(Inst, Size, memoryObject, Index - SectionVMA, DebugOut, nulls())) { - uint64_t addr; - if (error(i->getAddress(addr))) break; - outs() << format("%8x:\t", addr...

...t kvmi_vcpu_get_cpuid_reply rpl = {}; + __u32 function = 0; + __u32 index = 0; + int r; + + r = cmd_vcpu_get_cpuid(vm, function, index, &rpl); + TEST_ASSERT(r == 0, + "KVMI_VCPU_GET_CPUID failed, error %d(%s)\n", + -r, kvm_strerror(-r)); + + pr_info("cpuid(%u, %u) => eax 0x%.8x, ebx 0x%.8x, ecx 0x%.8x, edx 0x%.8x\n", + function, index, rpl.eax, rpl.ebx, rpl.ecx, rpl.edx); +} + static void test_introspection(struct kvm_vm *vm) { srandom(time(0)); @@ -1052,6 +1085,7 @@ static void test_introspection(struct kvm_vm *vm) test_cmd_vcpu_control_events(vm); tes...