Displaying 4 results from an estimated 4 matches for "8e20000".
2016 Aug 26
0
[PATCH v8 06/18] ARM: STi: DT: STiH407: Add FDMA driver dt nodes.
...407-family.dtsi
index d294e82..45cab30 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -821,5 +821,57 @@
clock-frequency = <600000000>;
st,syscfg = <&syscfg_core 0x224>;
};
+
+ /* fdma audio */
+ fdma0: dma-controller at 8e20000 {
+ compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
+ reg = <0x8e20000 0x8000>,
+ <0x8e30000 0x3000>,
+ <0x8e37000 0x1000>,
+ <0x8e38000 0x8000>;
+ reg-names = "slimcore", "dmem", "periphera...
2011 Feb 03
1
possible bug running Finale 2009 on Wine 1.2
...00- 8a20000 Deferred bmovrbar.fxt
PE 8a20000- 8a51000 Deferred optsinfo.fxt
PE 8a60000- 8ac4000 Deferred patbeams.fxt
PE 8ad0000- 8ae8000 Deferred moverests.fxt
PE 8c00000- 8c0a000 Deferred cebeams.fxt
PE 8e20000- 8e28000 Deferred flatbm.fxt
PE 9040000- 9052000 Deferred rhyths32.fxt
PE 9170000- 9180000 Deferred midlinestemdirections.fxt
PE 9290000- 929a000 Deferred hsledg32.fxt
PE 94b0000- 94c0000 Deferred defaultrests....
2016 Aug 26
32
[PATCH v8 00/18] Add support for FDMA DMA controller and slim core rproc found on STi chipsets
Hi Vinod, Bjorn, Patrice,
This patchset adds support for the Flexible Direct Memory Access (FDMA) core
found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU
with a dedicated firmware. It is a general purpose DMA controller supporting
16 independent channels and data can be moved from memory to memory or between
memory and paced latency critical real time targets.
After quite
2016 Aug 26
32
[PATCH v8 00/18] Add support for FDMA DMA controller and slim core rproc found on STi chipsets
Hi Vinod, Bjorn, Patrice,
This patchset adds support for the Flexible Direct Memory Access (FDMA) core
found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU
with a dedicated firmware. It is a general purpose DMA controller supporting
16 independent channels and data can be moved from memory to memory or between
memory and paced latency critical real time targets.
After quite