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Displaying 3 results from an estimated 3 matches for "8db91fc4".

2012 Jun 14
1
[LLVMdev] non-SSA IR generation
...LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120613/8db91fc4/attachment.html>
2012 Jun 13
0
[LLVMdev] non-SSA IR generation
Hi Amruth, If you do not specify any optimization flag for 'clang' and do not run 'opt -mem2reg' pass on the generated IR file, it is in non-SSA form. However, many variables stay in memory instead of registers in this case. Thanks, Jiesheng On Wed, Jun 13, 2012 at 1:17 PM, <amruth.rd at knights.ucf.edu> wrote: > I am experimenting with LLVM optimizer and found that
2012 Jun 13
3
[LLVMdev] non-SSA IR generation
I am experimenting with LLVM optimizer and found that the bit code file clang emits is already in SSA form, but I want to generate it in non-SSA form. Would you let me know if there is any way of doing it? Cheera,Amruth -------------- next part -------------- An HTML attachment was scrubbed... URL: