Displaying 1 result from an estimated 1 matches for "8d410810".
2015 Feb 18
2
[LLVMdev] How to specify displacement range of a target instruction to llc
Hi,
I'm working on a project that use llvm openrisc beckend (currently not part
of the upstream). Right now I'm looking at a bug where llc generates memory
instructions that has out-of-range displacement, for example
l.sb 37668(r1), r2 in which 37668 is a 17 bit signed integer, but the
instruction only allows 16 bit signed displacement. As a result, after
running through the