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2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...__________ LLVM Developers mailing list llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev <https://protect2.fireeye.com/v1/url?k=52e18446-0c413e28-52e1c4dd-86b1886cfa 64-f424e731a80348bd&q=1&e=238953c8-f0ec-4510-8c97-620bfb03d5be&u=https%3A%2F %2Flists.llvm.org%2Fcgi-bin%2Fmailman%2Flistinfo%2Fllvm-dev> -- ---------------------------------------------------------------------- Dominik Montada Email: dominik.montada at hightec-rt.com <mailto:dominik.montada at hightec-rt.com> Hi...
2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
Hi, I am in the process of porting our target to GlobalISel, and have encountered a problem. Nearly all instructions in our instruction set make modifications to a CC register, and hence are defined as follows: let ..., Defs = [CCReg] in def shfts_a32_imm7: Instruction<(outs OurRC:$dst), ...>; What's more, many of these instructions have patterns where the instruction itself
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...t Ã…kerlund _______________________________________________ LLVM Developers mailing list <mailto:llvm-dev at lists.llvm.org> llvm-dev at lists.llvm.org <https://protect2.fireeye.com/v1/url?k=52e18446-0c413e28-52e1c4dd-86b1886cfa 64-f424e731a80348bd&q=1&e=238953c8-f0ec-4510-8c97-620bfb03d5be&u=https%3A%2F %2Flists.llvm.org%2Fcgi-bin%2Fmailman%2Flistinfo%2Fllvm-dev> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- ---------------------------------------------------------------------- Dominik Montada Email: <mailto:dominik.montada at...