Displaying 2 results from an estimated 2 matches for "8b8c8d280ab2".
2018 Sep 07
1
[PATCH] PCI: Reprogram bridge prefetch registers on resume
...But at that time, we restored the config space in order of dword 0, 1,
2, ... 15, which means we restored the command register before the
BARs and windows, and it's conceivable that the problem was the
ordering, not the rewriting of the same value.
Only a week later, we reversed the order with 8b8c8d280ab2 ("[PATCH]
PCI: reverse pci config space restore order") [2], which seems like a
good idea and even includes a spec reference. I found similar
language in the Intel ICH 10 datasheet, sec 14.1.3 [3].
So it seems reasonable to me to try writing them unconditionally in
reverse order (the sa...
2018 Sep 07
9
[PATCH] PCI: Reprogram bridge prefetch registers on resume
On 38+ Intel-based Asus products, the nvidia GPU becomes unusable
after S3 suspend/resume. The affected products include multiple
generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs
many errors such as:
fifo: fault 00 [READ] at 0000005555555000 engine 00 [GR] client 04 [HUB/FE] reason 4a [] on channel -1 [007fa91000 unknown]
DRM: failed to idle channel 0 [DRM]