Displaying 3 results from an estimated 3 matches for "8b869c1f".
2013 Nov 12
2
[LLVMdev] Limit loop vectorizer to SSE
On 12 November 2013 15:14, Frank Winter <fwinter at jlab.org> wrote:
> I am asking because the option 'force-vector-width' is too restrictive.
> I would like to leave open the possibility to use vector width 2.
I was about to say that, and you saved us both one cycle. ;)
What you could do is to force an architecture that doesn't have AVX, only
SSE. I'm not sure how
2013 Nov 12
0
[LLVMdev] Limit loop vectorizer to SSE
.. forcing the vector size to 4 does not prevent using AVX. I just hit
the following:
LV: We can vectorize this loop!
LV: Found trip count: 4
LV: The Widest type: 64 bits.
LV: The Widest register is: 256 bits.
LV: Using user VF 4.
Looks like I have to disable AVX somehow. (Which is sad on its own.)
Frank
On 12/11/13 10:34, Renato Golin wrote:
> On 12 November 2013 15:14, Frank Winter
2013 Nov 12
2
[LLVMdev] Limit loop vectorizer to SSE
...sure how you're doing it in the JIT.
I'm also not sure how to set target parameters in JIT, you'll have to do
that by hand.
cheers,
--renato
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