search for: 86a31a8e1e51

...ware_get(struct nvkm_device *device, const char *fwname, > + const struct firmware **fw); > + > +void nvkm_firmware_put(const struct firmware *fw); > + > +#endif > diff --git a/drm/nouveau/nvkm/core/Kbuild b/drm/nouveau/nvkm/core/Kbuild > index 7f66963f305c..86a31a8e1e51 100644 > --- a/drm/nouveau/nvkm/core/Kbuild > +++ b/drm/nouveau/nvkm/core/Kbuild > @@ -2,6 +2,7 @@ nvkm-y := nvkm/core/client.o > nvkm-y += nvkm/core/engine.o > nvkm-y += nvkm/core/enum.o > nvkm-y += nvkm/core/event.o > +nvkm-y += nvkm/core/firmware.o > nvkm-y += nvkm/co...

...+#include <core/device.h> + +int nvkm_firmware_get(struct nvkm_device *device, const char *fwname, + const struct firmware **fw); + +void nvkm_firmware_put(const struct firmware *fw); + +#endif diff --git a/drm/nouveau/nvkm/core/Kbuild b/drm/nouveau/nvkm/core/Kbuild index 7f66963f305c..86a31a8e1e51 100644 --- a/drm/nouveau/nvkm/core/Kbuild +++ b/drm/nouveau/nvkm/core/Kbuild @@ -2,6 +2,7 @@ nvkm-y := nvkm/core/client.o nvkm-y += nvkm/core/engine.o nvkm-y += nvkm/core/enum.o nvkm-y += nvkm/core/event.o +nvkm-y += nvkm/core/firmware.o nvkm-y += nvkm/core/gpuobj.o nvkm-y += nvkm/core/ioctl.o...

...*device, const char *fwname, >> + const struct firmware **fw); >> + >> +void nvkm_firmware_put(const struct firmware *fw); >> + >> +#endif >> diff --git a/drm/nouveau/nvkm/core/Kbuild b/drm/nouveau/nvkm/core/Kbuild >> index 7f66963f305c..86a31a8e1e51 100644 >> --- a/drm/nouveau/nvkm/core/Kbuild >> +++ b/drm/nouveau/nvkm/core/Kbuild >> @@ -2,6 +2,7 @@ nvkm-y := nvkm/core/client.o >> nvkm-y += nvkm/core/engine.o >> nvkm-y += nvkm/core/enum.o >> nvkm-y += nvkm/core/event.o >> +nvkm-y += nvkm/core/firmwa...

This patchset centralizes the firmware-loading procedure to one set of functions instead of having each engine load its firmware as it pleases. This helps ensure that all firmware comes from the same place, namely nvidia/<chip>/. This changes where the firmware is fetched from for falcon/xtensa/bios, but these locations never seemed to have been official anyway. Also for most (all?) chips

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,