Displaying 10 results from an estimated 10 matches for "848b".
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848
2018 Apr 03
0
Sharding problem - multiple shard copies with mismatching gfids
...ac40c85/images/_remove_me_9a0660e1-bd86-47ea-8e09-865c14f11f26/e2645bd1-a7f3-4cbd-9036-3d3cbc7204cd.meta
found on cached subvol ovirt-350-zone1-replicate-5
[2018-04-03 02:07:57.967489] I [MSGID: 109070]
[dht-common.c:2796:dht_lookup_linkfile_cbk] 0-ovirt-350-zone1-dht:
Lookup of /.shard/927c6620-848b-4064-8c88-68a332b645c2.7 on
ovirt-350-zone1-replicate-3 (following linkfile) failed ,gfid =
00000000-0000-0000-0000-000000000000 [No such file or directory]
[2018-04-03 02:07:57.974815] I [MSGID: 109069]
[dht-common.c:2095:dht_lookup_unlink_stale_linkto_cbk]
0-ovirt-350-zone1-dht: Returned with...
2018 Apr 06
1
Sharding problem - multiple shard copies with mismatching gfids
...> me_9a0660e1-bd86-47ea-8e09-865c14f11f26/e2645bd1-a7f3-4cbd-9036-3d3cbc7204cd.meta
> found on cached subvol ovirt-350-zone1-replicate-5
> [2018-04-03 02:07:57.967489] I [MSGID: 109070]
> [dht-common.c:2796:dht_lookup_linkfile_cbk] 0-ovirt-350-zone1-dht: Lookup
> of /.shard/927c6620-848b-4064-8c88-68a332b645c2.7 on
> ovirt-350-zone1-replicate-3 (following linkfile) failed ,gfid =
> 00000000-0000-0000-0000-000000000000 [No such file or directory]
> [2018-04-03 02:07:57.974815] I [MSGID: 109069]
> [dht-common.c:2095:dht_lookup_unlink_stale_linkto_cbk]
> 0-ovirt-350-zon...
2018 Mar 26
1
Sharding problem - multiple shard copies with mismatching gfids
Ian,
Do you've a reproducer for this bug? If not a specific one, a general
outline of what operations where done on the file will help.
regards,
Raghavendra
On Mon, Mar 26, 2018 at 12:55 PM, Raghavendra Gowdappa <rgowdapp at redhat.com>
wrote:
>
>
> On Mon, Mar 26, 2018 at 12:40 PM, Krutika Dhananjay <kdhananj at redhat.com>
> wrote:
>
>> The gfid mismatch
2018 Mar 26
3
Sharding problem - multiple shard copies with mismatching gfids
On Mon, Mar 26, 2018 at 12:40 PM, Krutika Dhananjay <kdhananj at redhat.com>
wrote:
> The gfid mismatch here is between the shard and its "link-to" file, the
> creation of which happens at a layer below that of shard translator on the
> stack.
>
> Adding DHT devs to take a look.
>
Thanks Krutika. I assume shard doesn't do any dentry operations like
rename,
2014 Aug 19
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...on for the
> subsequent uses of Reg5.
>
> You can give it a try and see how it goes.
I tried setting isUndef to trie when handling INSERT_SUBREG in
TwoAddressInstructioPass.cpp, but then I run into stuff like this instead:
832B %vreg50:hi16<def,read-undef> = COPY %vreg0
848B ...
864B %vreg19<def,dead> = COPY %vreg50
880B %vreg19:lo16<def,read-undef> = COPY %vreg73
896B ...
912B mv_a32_r16_rmod1 %vreg19, %vreg20
...
*** Bad machine code: Multiple connected components in live interval ***
- function:...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...5<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
register: %vreg45 +[800r,816r:0)
816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1
register: %vreg46 +[832r,848r:0)
848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>, %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
BB#3:# der...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...0_Reg32:%vreg45
> R600_Reg128:%vreg1
> register: %vreg45 +[800r,816r:0)
> 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
> 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46
> R600_Reg128:%vreg1
> register: %vreg46 +[832r,848r:0)
> 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
> 864BRETURN %T1_W<imp-use,kill>, %T1_Z<imp-use,kill>,
> %T1_Y<imp-use,kill>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>,
> %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,ki...
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi,
I have a problem regarding sub-register definitions and LiveIntervals on
our target. When a subregister is defined, other parts of the register
are always left untouched - they are neither read or def:ed.
It however seems that Codegen treats subregister definitions as somehow
clobbering the whole register.
The SSA-code looks like this after isel:
(Reg0 and Reg1 are 16bit registers. Reg2,
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...; 800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
> 816B%vreg33<def> = IMPLICIT_DEF; R600_Reg128:%vreg33
> 832B%vreg32<def,tied1> = INSERT_SUBREG %vreg33<tied0>, %vreg31<kill>, sel_x; R600_Reg128:%vreg32,%vreg33 R600_Reg32:%vreg31
> 848B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
> 864B%vreg35<def,tied1> = INSERT_SUBREG %vreg32<tied0>, %vreg34<kill>, sel_y; R600_Reg128:%vreg35,%vreg32 R600_Reg32:%vreg34
> 880B%vreg36<def,tied1> = INSERT_SUBREG %vreg35<tied0>, %vr...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ing to CFG: BB#1
800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
816B%vreg33<def> = IMPLICIT_DEF; R600_Reg128:%vreg33
832B%vreg32<def,tied1> = INSERT_SUBREG %vreg33<tied0>, %vreg31<kill>, sel_x; R600_Reg128:%vreg32,%vreg33 R600_Reg32:%vreg31
848B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
864B%vreg35<def,tied1> = INSERT_SUBREG %vreg32<tied0>, %vreg34<kill>, sel_y; R600_Reg128:%vreg35,%vreg32 R600_Reg32:%vreg34
880B%vreg36<def,tied1> = INSERT_SUBREG %vreg35<tied0>, %vreg5, sel_z...