Displaying 6 results from an estimated 6 matches for "842a".
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2017 Jul 11
8
[LLD] Linker Relaxation
...t main(){
foo(10);
return 0;
}
After compiling to a .o with -O2 -march=RV32IC we get (just looking at foo)
00000000 <foo>:
0: 1141 addi sp,sp,-16
2: c422 sw s0,8(sp)
4: c606 sw ra,12(sp)
6: 06300793 li a5,99
a: 842a mv s0,a0
c: 00a7cb63 blt a5,a0,22 <.L2>
10: 85aa mv a1,a0
12: 00000537 lui a0,0x0
16: 00050513 mv a0,a0
1a: 00000317 auipc t1,0x0
1e: 000300e7 jalr t1
00000022 <.L2>:
22: 40b2...
2017 Jul 11
4
[LLD] Linker Relaxation
...2 -march=RV32IC we get (just looking at
>> foo)
>>
>> 00000000 <foo>:
>> 0: 1141 addi sp,sp,-16
>> 2: c422 sw s0,8(sp)
>> 4: c606 sw ra,12(sp)
>> 6: 06300793 li a5,99
>> a: 842a mv s0,a0
>> c: 00a7cb63 blt a5,a0,22 <.L2>
>> 10: 85aa mv a1,a0
>> 12: 00000537 lui a0,0x0
>> 16: 00050513 mv a0,a0
>> 1a: 00000317 auipc t1,0x0
>> 1e: 000300e7 j...
2017 Jul 11
2
[LLD] Linker Relaxation
Hi,
Does lld support linker relaxation that may shrink code size? As far
as I see lld seems to assume that the content of input sections to be
fixed other than patching up relocations, but I believe some targets
may benefit the extra optimization opportunity with relaxation.
Specifically, I'm currently working on adding support for RISC-V in
lld, and RISC-V heavily relies on linker relaxation
2020 Aug 21
0
[PATCH] vdpa/mlx5: Avoid warnings about shifts on 32-bit platforms
...or supported mlx5 devices")
> Link: https://github.com/ClangBuiltLinux/linux/issues/1140
> Signed-off-by: Nathan Chancellor <natechancellor at gmail.com>
Reported-by: Randy Dunlap <rdunlap at infradead.org>
on 2020-AUG-10 for i386:
https://lore.kernel.org/linux-next/5a7a0e6d-842a-78f6-aeac-c5b4c27b7186 at infradead.org/
:(
Acked-by: Randy Dunlap <rdunlap at infradead.org> # build-tested
Thanks.
> ---
> drivers/vdpa/mlx5/net/mlx5_vnet.c | 50 +++++++++++++++----------------
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/drivers...
2020 Aug 21
3
[PATCH] vdpa/mlx5: Avoid warnings about shifts on 32-bit platforms
Clang warns several times when building for 32-bit ARM along the lines
of:
drivers/vdpa/mlx5/net/mlx5_vnet.c:1462:31: warning: shift count >= width
of type [-Wshift-count-overflow]
ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1);
^~~~~~~~~~~~~~~~~~~~~~~
This is related to the BIT macro, which uses an unsigned long literal,
2020 Aug 21
3
[PATCH] vdpa/mlx5: Avoid warnings about shifts on 32-bit platforms
Clang warns several times when building for 32-bit ARM along the lines
of:
drivers/vdpa/mlx5/net/mlx5_vnet.c:1462:31: warning: shift count >= width
of type [-Wshift-count-overflow]
ndev->mvdev.mlx_features |= BIT(VIRTIO_F_VERSION_1);
^~~~~~~~~~~~~~~~~~~~~~~
This is related to the BIT macro, which uses an unsigned long literal,