Displaying 1 result from an estimated 1 matches for "8363eb5c".
2012 Apr 27
1
[LLVMdev] PreRASched
Hi,
I wonder when the preRASched pass is planned to be available?
I wonder how one would best try to implement a pass in between RegCoalescer and RA. After RegCoalescer, the LiveVariables information seems broken (there are no Kills anywhere), and LiveVariables can't be rerun after SSA form is left. So, how could one rebuild LiveIntevals? For register allocation purposes - what would be the