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...the MCRegAliasIterator to dynamically compute the register aliases. The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation seems to imply this is a safe assumption and I haven't found a client that requires these att...

...3 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1 register: %vreg44 +[768r,784r:0) 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1 register: %vreg45 +[800r,816r:0) 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1 register: %vreg46 +[832r,848r:0) 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46 864BRETURN %T1_W<imp-use,kill>, %T1...

...1:sel_y; R600_Reg32:%vreg44 > R600_Reg128:%vreg1 > register: %vreg44 +[768r,784r:0) > 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44 > 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 > R600_Reg128:%vreg1 > register: %vreg45 +[800r,816r:0) > 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45 > 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 > R600_Reg128:%vreg1 > register: %vreg46 +[832r,848r:0) > 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46 > 864BRETURN %T1_...

LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also

...; R600_Reg32:%vreg46 R600_Reg128:%vreg1 > 752B%T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46 > 768BRETURN > > 784BBB#3: derived from LLVM BB %41 > Predecessors according to CFG: BB#1 > 800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 > 816B%vreg33<def> = IMPLICIT_DEF; R600_Reg128:%vreg33 > 832B%vreg32<def,tied1> = INSERT_SUBREG %vreg33<tied0>, %vreg31<kill>, sel_x; R600_Reg128:%vreg32,%vreg33 R600_Reg32:%vreg31 > 848B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > 864B%v...

...eg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 R600_Reg128:%vreg1 752B%T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46 768BRETURN 784BBB#3: derived from LLVM BB %41    Predecessors according to CFG: BB#1 800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 816B%vreg33<def> = IMPLICIT_DEF; R600_Reg128:%vreg33 832B%vreg32<def,tied1> = INSERT_SUBREG %vreg33<tied0>, %vreg31<kill>, sel_x; R600_Reg128:%vreg32,%vreg33 R600_Reg32:%vreg31 848B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 864B%vreg35<def,ti...