Displaying 20 results from an estimated 24 matches for "80r".
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2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
..."<90>w\n "
mov r0, r5
mov r1, r4
mov r2, r6
ldr r6, .LCPI0_0
blx r6
mov r0, r5
mov r1, r5
mov r2, r4
blx r6
regalloc dump (attached) shows:
Inline spilling tGPR:%9 [80r,152r:0) 0 at 80r weight:3.209746e-03
>From original %3
also spill snippet %8 [152r,232r:0) 0 at 152r weight:2.104167e-03
tBL 14, $noreg, &bar, implicit-def $lr, implicit $sp, implicit
killed $r0, implicit killed $r1, implicit killed $r2
folded: 144r tBL 14, $noreg, &am...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...0r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+00
%1 [32r,304r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0) 0 at 16r weight:0.000000e+00
%3 [80r,336r:0) 0 at 80r weight:0.000000e+00
RegMasks: 144r 240r 336r
********** MACHINEINSTRS **********
# Machine code for function uECC_shared_secret: NoPHIs, TracksLiveness
Constant Pool:
cp#0: @foo, align=4
Function Live Ins: $r0 in %0, $r1 in %1, $r2 in %2
0B bb.0.entry:
liveins: $r0, $r1, $r2...
2013 Oct 07
1
[LLVMdev] Subregister liveness tracking
...:ssub_0<def,read-undef> = ...
32B %vreg0:ssub_1<def> = ...
48B = %vreg0
64B = %vreg0:ssub_0
80B %vreg0 = ...
96B = %vreg0:ssub_1
will be represented as the following live range(s):
Common LiveRange: [16r,32r)[32r,64r),[80r,96r)
SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d)
SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r)
Patches/Changes:
* Moves live range management code in the LiveInterval class to a new
class LiveRange, move the previous LiveRange class (which was just a
single
inter...
2013 Oct 08
2
[LLVMdev] Subregister liveness tracking
...<def> = ...
> 48B = %vreg0
> 64B = %vreg0:ssub_0
> 80B %vreg0 = ...
> 96B = %vreg0:ssub_1
>
> will be represented as the following live range(s):
>
> Common LiveRange: [16r,32r)[32r,64r),[80r,96r)
> SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d)
> SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r)
>
> Patches/Changes:
> * Moves live range management code in the LiveInterval class to a new
> class LiveRange, move the previous Live...
2013 Oct 08
0
[LLVMdev] Subregister liveness tracking
...gt; = ...
>> 48B = %vreg0
>> 64B = %vreg0:ssub_0
>> 80B %vreg0 = ...
>> 96B = %vreg0:ssub_1
>>
>> will be represented as the following live range(s):
>>
>> Common LiveRange: [16r,32r)[32r,64r),[80r,96r)
>> SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d)
>> SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r)
>>
>> Patches/Changes:
>> * Moves live range management code in the LiveInterval class to a new
>> class LiveRange, move the previous...
2013 Oct 10
1
[LLVMdev] Missing optimization - constant parameter
...th %RDI
> Can only merge into reserved registers.
> Remat: %RDI<def> = MOV64ri 12345123400
> Shrink: [32r,64r:0) 0 at 32r
> Shrunk: [32r,48r:0) 0 at 32r
> Trying to inflate 0 regs.
> ********** INTERVALS **********
> %vreg0 = [32r,48r:0) 0 at 32r
> RegMasks: 80r
>
> Jakob, what does "can only merge into reserved registers" mean in this instance. I don't see any reason for it not to do the merge.
The coalescer won’t merge virtual and allocatable physical registers because that will extend the live range of the physical registers, const...
2018 Sep 11
2
linear-scan RA
...NOOP implicit %0
> %1 = COPY %0
> JMP_1 %bb.3
>
> bb.3:
> NOOP implicit %1
>
>
>
> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> ********** INTERVALS **********
> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
> RegMasks:
> ********** MACHINEINSTRS **********
> # Machine code for function somefunc: NoPHIs
>
> 0B bb.0:
> successors: %bb.2(0x80000000); %bb.2(100.00%)
>
> 16B %0:gr32 = MOV3...
2013 Oct 10
0
[LLVMdev] Missing optimization - constant parameter
...g0
Considering merging %vreg0 with %RDI
Can only merge into reserved registers.
Remat: %RDI<def> = MOV64ri 12345123400
Shrink: [32r,64r:0) 0 at 32r
Shrunk: [32r,48r:0) 0 at 32r
Trying to inflate 0 regs.
********** INTERVALS **********
%vreg0 = [32r,48r:0) 0 at 32r
RegMasks: 80r
Jakob, what does "can only merge into reserved registers" mean in this
instance. I don't see any reason for it not to do the merge.
On Mon, Aug 5, 2013 at 11:19 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On Aug 5, 2013, at 8:34 AM, Maurice Marks <mau...
2012 Apr 18
0
Error in eval when using contrast and nlme
...4L, 4L, 4L, 4L, 4L, 4L, 4L, 4L, 5L, 5L, 5L, 5L, 5L, 5L, 5L,
5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L,
5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L, 5L,
5L, 5L, 5L, 5L, 5L), .Label = c("20r", "40r",
"80r", "neg40r", "neg80r"), class = "factor"),
scanner = structure(c(1L, 1L, 1L, 1L, 1L, 1L, 1L, 1L, 2L,
1L, 1L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 1L, 1L, 1L,
2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L, 2L,
2L, 2L, 2L, 1L, 1L, 1L, 1L,...
2013 Aug 05
2
[LLVMdev] Missing optimization - constant parameter
On Aug 5, 2013, at 8:34 AM, Maurice Marks <maurice.marks at gmail.com> wrote:
> Are you sure that's it? I commented that block out, rebuilt llvm 3.3, and it still duplicates the constant.
> My concern is that long constant loads increase code size and if they can be avoided by better targeting it would be a win. My project's application of llvm tends to use a lot of long
2013 Oct 09
4
[LLVMdev] Subregister liveness tracking
...; = ...
>> 48B = %vreg0
>> 64B = %vreg0:ssub_0
>> 80B %vreg0 = ...
>> 96B = %vreg0:ssub_1
>>
>> will be represented as the following live range(s):
>>
>> Common LiveRange: [16r,32r)[32r,64r),[80r,96r)
>> SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d)
>> SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r)
>>
>> Patches/Changes:
>> * Moves live range management code in the LiveInterval class to a new
>> class LiveRange, move the previous...
2018 Sep 11
2
linear-scan RA
...JMP_1 %bb.3
> >
> > bb.3:
> > NOOP implicit %1
> >
> >
> >
> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> > ********** INTERVALS **********
> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> > RegMasks:
> > ********** MACHINEINSTRS **********
> > # Machine code for function somefunc: NoPHIs
> >
> > 0B bb.0:
> > successors: %bb.2(0x80000000); %bb.2(100.00%)...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2020 Apr 15
2
[ARM] Register pressure with -mthumb forces register reload before each call
...0, r5
> mov r1, r4
> mov r2, r6
> ldr r6, .LCPI0_0
> blx r6
> mov r0, r5
> mov r1, r5
> mov r2, r4
> blx r6
>
> regalloc dump (attached) shows:
> Inline spilling tGPR:%9 [80r,152r:0) 0 at 80r weight:3.209746e-03
> From original %3
> also spill snippet %8 [152r,232r:0) 0 at 152r weight:2.104167e-03
> tBL 14, $noreg, &bar, implicit-def $lr, implicit $sp, implicit
> killed $r0, implicit killed $r1, implicit killed $r2
> folded: 144r...
2018 Sep 11
2
linear-scan RA
...implicit %1
> >> >
> >> >
> >> >
> >> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> >> > ********** INTERVALS **********
> >> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> >> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> >> > RegMasks:
> >> > ********** MACHINEINSTRS **********
> >> > # Machine code for function somefunc: NoPHIs
> >> >
> >> > 0B bb.0:
> >&g...
2018 Sep 11
2
linear-scan RA
...t;>>>>
>>>>>>
>>>>>> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
>>>>>> ********** INTERVALS **********
>>>>>> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
>>>>>> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
>>>>>> RegMasks:
>>>>>> ********** MACHINEINSTRS **********
>>>>>> # Machine code for function somefunc: NoPHIs
>>>>>>
>>>>>...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...B#0: # derived from entry
16B %vreg0<def> = COPY %R2<kill>; GPRegs:%vreg0
register: %vreg0 +[16r,32r:0)
32B STWi13 <fi#1>, 0, %vreg0<kill>; mem:ST4[%a.addr] GPRegs:%vreg0
BB#1: # derived from if.then
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
register: %vreg3 +[64r,80r:0)
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
BB#2: # derived from if.else
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
register: %vreg2 +[112r,128r:0)
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
BB#3: # derived from ret...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...er: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef...