Displaying 20 results from an estimated 41 matches for "80b".
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2020 Sep 05
3
Samba AD not resolving external names
...slookup google.com
;; Got SERVFAIL reply from 192.168.4.5, trying next server
Server: 8.8.8.8
Address: 8.8.8.8#53
Non-authoritative answer:
Name: google.com
Address: 216.58.195.78
;; Got SERVFAIL reply from 192.168.4.5, trying next server
Name: google.com
Address: 2607:f8b0:4005:80b::200e
2013 Aug 02
0
[LLVMdev] Missing optimization - constant parameter
...%vreg1<def> = MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5],
%noreg; mem:LD8[GOT] GR64:%vreg1
48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
96B %RDI<def> = COPY %vreg2; GR64:%vreg2
112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
%RDI<imp-use,kill>
into
0...
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
For the little C test program where a constant is stored in memory and
also
used as a parameter:
#include <stdint.h>
uint64_t val, *p;
extern uint64_t xtr( uint64_t);
uint64_t caller() {
uint64_t x;
p = &val;
x = 12345123400L;
*p = x;
return xtr(x);
}
clang (3.2, 3.3 and svn) generates the following X86 code (at -O3):
caller:
movq
2013 Aug 02
2
[LLVMdev] Missing optimization - constant parameter
...= MOV64rm %RIP, 1, %noreg, <ga:@p>[TF=5],
> %noreg; mem:LD8[GOT] GR64:%vreg1
> 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
> mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
> %RDI<imp-u...
2020 Nov 19
1
Problems with undef subranges in identity copies
...rased and the interval is updated
(https://github.com/llvm/llvm-project/blob/523cc097fdafa1bb60373dcc70df7dfd31551f56/llvm/lib/CodeGen/RegisterCoalescer.cpp#L1871),
the new live interval looks like this:
%0 [16r,32B:2)[32B,96r:0)[96r,128B:1) 0 at 32B-phi 1 at 96r 2 at 16r
L0000000000000003 [32B,80B:0) 0 at 32B-phi // sub0
This remaining [32B,80B:0) across %bb.1 is a fake phi-only segment. If
I freshly recompute LiveIntervals, the subrange is empty as it should
be. The verifier doesn't care about this, however it does end up
confusing RenameIndependentSubregs. After RenameIndependentSubr...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
..._A_iSLo 1077936128; FPUaOffsetClass:%vreg2
48B %vreg3<def> = FMUL_A_oo %vreg0, %vreg2, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg3 FPUaOffsetClass:%vreg0,%vreg2
64B %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
80B %vreg5<def> = MOVSUTO_A_iSLo 1056964608; FPUaOffsetClass:%vreg5
96B %vreg6<def> = FMUL_A_oo %vreg0, %vreg5, %RFLAGA<imp-def,dead>; FPUaROUTMULRegisterClass:%vreg6 FPUaOffsetClass:%vreg0,%vreg5
112B %vreg7<def> = COPY %vreg6; FPUaOffsetClass...
2020 Sep 05
3
Samba AD not resolving external names
...;> Server: 8.8.8.8
>> Address: 8.8.8.8#53
>>
>> Non-authoritative answer:
>> Name: google.com
>> Address: 216.58.195.78
>> ;; Got SERVFAIL reply from 192.168.4.5, trying next server
>> Name: google.com
>> Address: 2607:f8b0:4005:80b::200e
>
> Is this on the DC or a client ?
>
> On my DC I get this:
>
> adminuser at kdsdc:~$ nslookup google.com <http://google.com/>
> Server: 192.168.0.10
> Address: 192.168.0.10#53
>
> Non-authoritative answer:
> Name: google.com <http:/...
2004 Oct 21
2
how to read the stats
...es 0)
qdisc sfq 30: limit 128p quantum 1514b flows 128/1024 perturb 10sec
Sent 495316458 bytes 541852 pkts (dropped 9303, overlimits 0 requeues
0)
backlog 46p
>>>> This I belive is my parent class is has access to the whole 64Kbit
class htb 1:1 root rate 64Kbit ceil 64Kbit burst 80b/8 mpu 0b overhead
0b cburst 1507b/8 mpu 0b overhead 0b level 7
Sent 542500093 bytes 1342581 pkts (dropped 0, overlimits 0 requeues 0)
rate 7201bit 20pps
lended: 322826 borrowed: 0 giants: 0
tokens: -228224 ctokens: -45568
class htb 1:10 parent 1:1 leaf 10: prio 1 quantum 8 rate 57Kbit ceil...
2013 Aug 05
0
[LLVMdev] Missing optimization - constant parameter
...g, <ga:@p>[TF=5],
> > %noreg; mem:LD8[GOT] GR64:%vreg1
> > 48B MOV64mr %vreg1, 1, %noreg, 0, %noreg, %vreg0;
> > mem:ST8[@p](tbaa=!"any pointer") GR64:%vreg1,%vreg0
> > 64B %vreg2<def> = MOV64ri 12345123400; GR64:%vreg2
> > 80B MOV64mr %vreg0, 1, %noreg, 0, %noreg, %vreg2;
> > mem:ST8[@val](tbaa=!"long long") GR64:%vreg0,%vreg2
> > 96B %RDI<def> = COPY %vreg2; GR64:%vreg2
> > 112B TCRETURNdi64 <ga:@xtr>, 0, <regmask>, %RSP<imp-use>,
>...
2020 Apr 16
2
Need help figuring out a isNopCopy() assert
...0B bb.0.entry:
liveins: $r4
16B %1:gprc_and_gprc_nor0 = COPY $r4
32B %2:gprc = SPELWZ 0, undef %3:gprc_and_gprc_nor0 :: (load 4
from `float* undef`) 40B %5:gprc = SPELWZ 0, killed
%1:gprc_and_gprc_nor0 :: (load 4 from %ir.b1) 48B %4:sperc = COPY
killed %2:gprc 80B %6:sperc = COPY killed %5:gprc
...
MCP: Copy is a deletion candidate: renamable $s29 = COPY killed
renamable $r4
MCP: Copy is used - not dead: renamable $s29 = COPY
killed renamable $r4
MCP: Copy is used - not dead: renamable $s29 = COPY killed renamable
$r4
$s29 is a SPE register (6...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...de for function push: Post SSA
Function Live Outs: %R0
0B BB#0: derived from LLVM BB %entry
16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
Successors according to CFG: BB#1
48B BB#1: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#0 BB#1
80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
IntRegs:%vreg10,%vreg9
112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRe...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...n Live Outs: %R0
>
> 0B BB#0: derived from LLVM BB %entry
> 16B %vreg9<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg9
> Successors according to CFG: BB#1
>
> 48B BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0 BB#1
> 80B %vreg1<def> = COPY %vreg10<kill>; IntRegs:%vreg1,%vreg10
> 96B %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in]
> IntRegs:%vreg10,%vreg9
> 112B %vreg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQr...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...f> = LDriw %vreg0, 0;
mem:LD4[%a],IntRegs:%vreg1,%vreg0
48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
------------------------------------------------------------------
LDriw and LDriw_indexed load 32 -bit words. So %vreg1 and %vreg2 are both
32-bit virtual registers. Hexagon has register pairs and even-odd registers
can...
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...D4[%a]
> IntRegs:%vreg1,%vreg0
> 48B %vreg2<def> = LDriw_indexed %vreg0<kill>, 4;
> mem:LD4[%add.ptr] IntRegs:%vreg2,%vreg0
> 64B %vreg7<def> = COMBINE_rr %vreg2<kill>, %vreg1<kill>;
> DoubleRegs:%vreg7 IntRegs:%vreg2,%vreg1
> 80B %D0<def> = COPY %vreg7<kill>; DoubleRegs:%vreg7
> ------------------------------------------------------------------
> LDriw and LDriw_indexed load 32 -bit words. So %vreg1 and %vreg2 are both
> 32-bit virtual registers. Hexagon has register pairs and even-odd...
2020 Sep 05
1
Samba AD not resolving external names
...erver: 8.8.8.8
> > Address: 8.8.8.8#53
> >
> > Non-authoritative answer:
> > Name: google.com
> > Address: 216.58.195.78
> > ;; Got SERVFAIL reply from 192.168.4.5, trying next server
> > Name: google.com
> > Address: 2607:f8b0:4005:80b::200e
>
> Is this on the DC or a client ?
>
> On my DC I get this:
>
> adminuser at kdsdc:~$ nslookup google.com
> Server: 192.168.0.10
> Address: 192.168.0.10#53
>
> Non-authoritative answer:
> Name: google.com
> Address: 216.58.204.46
> Name:...
2020 Sep 05
0
Samba AD not resolving external names
...> Address: 8.8.8.8#53
> >>
> >> Non-authoritative answer:
> >> Name: google.com
> >> Address: 216.58.195.78
> >> ;; Got SERVFAIL reply from 192.168.4.5, trying next server
> >> Name: google.com
> >> Address: 2607:f8b0:4005:80b::200e
> >
> > Is this on the DC or a client ?
> >
> > On my DC I get this:
> >
> > adminuser at kdsdc:~$ nslookup google.com <http://google.com/>
> > Server: 192.168.0.10
> > Address: 192.168.0.10#53
> >
> > Non-authoritati...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...erived from LLVM BB %entry
Live Ins: %R2
16B %vreg0<def> = COPY %R2; GPRegs:%vreg0
32B STWi13 <fi#1>, 0, %vreg0; mem:ST4[%a.addr] GPRegs:%vreg0
48B %vreg1<def> = CMPri %vreg0, 0; CondRegs:%vreg1 GPRegs:%vreg0
64B BRcondrel %vreg1<kill>, <BB#2>; CondRegs:%vreg1
80B BRrel <BB#1>
Successors according to CFG: BB#1(12) BB#2(20)
96B BB#1: derived from LLVM BB %if.then
Predecessors according to CFG: BB#0
112B %vreg3<def> = MOVri 1; GPRegs:%vreg3
128B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
144B BRrel <...
2018 Sep 11
2
linear-scan RA
...de for function somefunc: NoPHIs
>
> 0B bb.0:
> successors: %bb.2(0x80000000); %bb.2(100.00%)
>
> 16B %0:gr32 = MOV32ri 42
> 32B JB_1 %bb.2, implicit undef $eflags
> 48B JMP_1 %bb.2
>
> 64B bb.1:
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 80B %1:gr32 = MOV32ri 17
> 96B JMP_1 %bb.3
>
> 112B bb.2:
> ; predecessors: %bb.0
> successors: %bb.3(0x80000000); %bb.3(100.00%)
>
> 128B NOOP implicit %0:gr32
> 144B %1:gr32 = COPY %0:gr32
> 160B JMP_1 %bb.3
>
> 176B bb.3:
> ; predecessors: %bb.1,...
2013 Oct 07
1
[LLVMdev] Subregister liveness tracking
...these changes you
can
have separate live ranges for subregisters of a virtual register. With
these
patches the following code:
16B %vreg0:ssub_0<def,read-undef> = ...
32B %vreg0:ssub_1<def> = ...
48B = %vreg0
64B = %vreg0:ssub_0
80B %vreg0 = ...
96B = %vreg0:ssub_1
will be represented as the following live range(s):
Common LiveRange: [16r,32r)[32r,64r),[80r,96r)
SubRange with Mask 0x0004 (=ssub_0): [16r,64r)[80r,80d)
SubRange with Mask 0x0008 (=ssub_1): [32r,48r)[80r,96r)
Patches/Changes:
* Moves live r...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the