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..._Reg32:%vreg43 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1 register: %vreg44 +[768r,784r:0) 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1 register: %vreg45 +[800r,816r:0) 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 R600_Reg128:%vreg1 register: %vreg46 +[832r,848r:0) 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46 864BRETURN %T1_W<imp-use,...

...f> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 > R600_Reg128:%vreg1 > register: %vreg44 +[768r,784r:0) > 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44 > 800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 > R600_Reg128:%vreg1 > register: %vreg45 +[800r,816r:0) > 816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45 > 832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46 > R600_Reg128:%vreg1 > register: %vreg46 +[832r,848r:0) > 848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46 &g...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2