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2010 Oct 13
0
[LLVMdev] [Q] x86 peephole deficiency
On Oct 13, 2010, at 11:22 AM, Gabor Greif wrote:
> Hi Chris,
>
> I had a look into MachineCSE, but it looks like MBB-oriented.
> The above problem is an inter-block one. Also MCSE seems
> to perform value numbering on virtual/physical registers, which
> does not map very well to status register bits that are implicitly
> defined.
> Any chance to recast this issue as a
2010 Oct 13
2
[LLVMdev] [Q] x86 peephole deficiency
Am 07.10.2010 um 19:50 schrieb Chris Lattner:
>
> On Oct 6, 2010, at 6:16 PM, Gabor Greif wrote:
>
>> Hi all,
>>
>> I am slowly working on a SwitchInst optimizer (http://llvm.org/
>> PR8125)
>> and now I am running into a deficiency of the x86
>> peephole optimizer (or jump-threader?). Here is what I get:
>>
>>
>> andl $3,