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On Jun 11, 2007, at 6:14 PM, Christopher Lamb wrote: > > What's the best way to get an SDNode through to DAG scheduling > without getting mangled during Lowering/ISel? What do you mean by "mangled"? Please clarify. > > When should subregs be flattened to actual registers: AsmPrinter? > Somewhere in LiveIntervals, during RegAlloc? You mean turning part of a

What's the best way to get an SDNode through to DAG scheduling without getting mangled during Lowering/ISel? When should subregs be flattened to actual registers: AsmPrinter? Somewhere in LiveIntervals, during RegAlloc? Is there are common API used to turn vregs into physregs that could be changed to flatten any subregs in a central location? -- Christopher Lamb

...s mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev -- Christopher Lamb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070612/7e9e7e7e/attachment.html>