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Hello everyone, We are working on extending RISC-V LLVM backend which will help us to achieve the goal of improving programmability in the second generation design of our open source RISC-V manycore processor (bjump.org/manycore). We started with supporting 64 bit pointers in RISCV 32 bit backend using address spaces and register pairs. We aim to support 64 bit pointers in address space 1 using

...//lists.llvm.org/pipermail/llvm-dev/2019-January/129089.html>. > CCing Dylan McKay in case he has any thoughts. > > Best, > > Alex > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190611/7d17dd42/attachment.html>