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Marcello Maggioni <hayarms at gmail.com> writes: > I'm working on an LLVM backend for a new target architecture which has > some instructions that when executed implicitly produce a result in a > particular register after a certain amount of cycles. > > The situation is this : > > 1: Execute instruction > 2: Wait for result > 3: Wait for result > 4: Wait

...ll sorts of instructions that > implicitly define registers and it handles this problem quite well. > > -David > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20121002/7bfa538e/attachment.html>

Hi, I'm working on an LLVM backend for a new target architecture which has some instructions that when executed implicitly produce a result in a particular register after a certain amount of cycles. The situation is this : 1: Execute instruction 2: Wait for result 3: Wait for result 4: Wait for result 5: Read from register The value in the special register needs to be protected until the