Displaying 10 results from an estimated 10 matches for "752b".
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2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
...back to sibling value after the loop. My apologies [vregs 76->111, 87->122].
1.
The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense.
selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02
...
queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r
queuing new interval: %vreg122 [68r,400B:0)[400...
2014 Dec 09
2
[LLVMdev] InlineSpiller.cpp bug?
...My apologies [vregs 76->111, 87->122].
>>
>> 1.
>> The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense.
>> selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02
>> …
>> queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r
>> queuing new interval:...
2014 Nov 21
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin,
I have tried to find a test case for an official target, but failed. It seems to be a rare case.
To do it, I added the 'else' clause in the following:
...
if (VNI->def == OrigVNI->def) {
DEBUG(dbgs() << "orig phi value\n");
SVI->second.DefByOrigPHI = true;
SVI->second.AllDefsAreReloads = false;
propagateSiblingValue(SVI);
continue;
2022 Jul 10
1
flac-dev Digest, Vol 191, Issue 7
...------------------------------------------------------
>
> Message: 1
> Date: Fri, 8 Jul 2022 14:16:33 +0200
> From: Robert Kausch <robert.kausch at freac.org>
> To: flac-dev at xiph.org
> Subject: Re: [flac-dev] slow on apple silicon?
> Message-ID: <b97549ba-844d-cc21-752b-5889e35819bd at freac.org>
> Content-Type: text/plain; charset=UTF-8; format=flowed
>
> Am 08.07.2022 um 09:26 schrieb Martijn van Beurden:
> > Op wo 6 jul. 2022 om 22:09 schreef Scott Brown <scottcbrown at gmail.com>:
> >
> > Same list of cputype errors
>...
2022 Sep 19
2
flac-dev Digest, Vol 191, Issue 7
...--------------------------
>>
>> Message: 1
>> Date: Fri, 8 Jul 2022 14:16:33 +0200
>> From: Robert Kausch <robert.kausch at freac.org>
>> To: flac-dev at xiph.org
>> Subject: Re: [flac-dev] slow on apple silicon?
>> Message-ID: <b97549ba-844d-cc21-752b-5889e35819bd at freac.org>
>> Content-Type: text/plain; charset=UTF-8; format=flowed
>>
>> Am 08.07.2022 um 09:26 schrieb Martijn van Beurden:
>> > Op wo 6 jul. 2022 om 22:09 schreef Scott Brown <scottcbrown at gmail.com>:
>> >
>> > Same lis...
2023 Feb 27
1
flac-dev Digest, Vol 191, Issue 7
...gt;>>
>>> Message: 1
>>> Date: Fri, 8 Jul 2022 14:16:33 +0200
>>> From: Robert Kausch <robert.kausch at freac.org>
>>> To: flac-dev at xiph.org
>>> Subject: Re: [flac-dev] slow on apple silicon?
>>> Message-ID: <b97549ba-844d-cc21-752b-5889e35819bd at freac.org>
>>> Content-Type: text/plain; charset=UTF-8; format=flowed
>>>
>>> Am 08.07.2022 um 09:26 schrieb Martijn van Beurden:
>>> > Op wo 6 jul. 2022 om 22:09 schreef Scott Brown <scottcbrown at gmail.com
>>> >:
>>&g...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...2<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 R600_Reg128:%vreg6
register: %vreg42 +[704r,720r:0)
720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 R600_Reg128:%vreg1
register: %vreg43 +[736r,752r:0)
752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
register: %vreg44 +[768r,784r:0)
784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg3...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ill>; R600_Reg32:%vreg42
> R600_Reg128:%vreg6
> register: %vreg42 +[704r,720r:0)
> 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
> 736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43
> R600_Reg128:%vreg1
> register: %vreg43 +[736r,752r:0)
> 752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
> 768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44
> R600_Reg128:%vreg1
> register: %vreg44 +[768r,784r:0)
> 784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
> 800B%vreg45<def> = CO...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...gt; 688B%T1_Y<def> = COPY %vreg44; R600_Reg32:%vreg44
> 704B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
> 720B%T1_Z<def> = COPY %vreg45; R600_Reg32:%vreg45
> 736B%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 R600_Reg128:%vreg1
> 752B%T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46
> 768BRETURN
>
> 784BBB#3: derived from LLVM BB %41
> Predecessors according to CFG: BB#1
> 800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
> 816B%vreg33<def> = IMPLICIT_DEF; R600_Reg12...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...eg44 R600_Reg128:%vreg1
688B%T1_Y<def> = COPY %vreg44; R600_Reg32:%vreg44
704B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
720B%T1_Z<def> = COPY %vreg45; R600_Reg32:%vreg45
736B%vreg46<def> = COPY %vreg1:sel_w; R600_Reg32:%vreg46 R600_Reg128:%vreg1
752B%T1_W<def> = COPY %vreg46; R600_Reg32:%vreg46
768BRETURN
784BBB#3: derived from LLVM BB %41
Predecessors according to CFG: BB#1
800B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
816B%vreg33<def> = IMPLICIT_DEF; R600_Reg128:%vreg33
832B%vreg32<def,t...