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2017 Feb 18
2
[RFC] Using Intel MPX to harden SafeStack
...|432249 | +--------------+---------+---------+---------+-------+ |458.sjeng|96593|192929|193121|251545 | +--------------+---------+---------+---------+-------+ |462.libquantum|32441|127065|127257|177545 | +--------------+---------+---------+---------+-------+ |464.h264ref|539713|638705|638897|736729 | +--------------+---------+---------+---------+-------+ |471.omnetpp|403521|527345|527537|597801 | +--------------+---------+---------+---------+-------+ |473.astar|31169|126225|126417|178105 | +--------------+---------+---------+---------+-------+ |483.xalancbmk |2358241|2725921 |2726113|29...
2008 Dec 24
6
Bug when using /dev/cciss/c0d2 as mdt/ost
I am trying to build lustre-1.6.6 against the pre-patched kernel downloaded from SUN. But as written in Operations manual, it creates rpms for 2.6.18-92.1.10.el5_lustrecustom. Is there a way to ask it not to append custom as extraversion. Running kernel is 2.6.18-92.1.10.el5_lustre.1.6.6smp. -- Regards-- Rishi Pathak National PARAM Supercomputing Facility Center for Development of Advanced
2017 Feb 08
4
[RFC] Using Intel MPX to harden SafeStack
Hi, I previously posted about using 32-bit X86 segmentation to harden SafeStack: http://lists.llvm.org/pipermail/llvm-dev/2016-May/100346.html That involves lowering the limits of the DS and ES segments that are used for ordinary data accesses while leaving the limit for SS, the stack segment, set to its maximum value. The safe stacks were clustered above the limits of DS and ES. Thus, by