Displaying 6 results from an estimated 6 matches for "704r".
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2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...+[432r,448B:0) phi-join +[448B,496r:1)
BB#1:# derived from
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
register: %vreg5 +[464r,592B:0) +[880B,992r:0)
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
register:...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...+[448B,496r:1)
> BB#1:# derived from
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
> register: %vreg5 +[464r,592B:0) +[880B,992r:0)
> 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
> register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0)
> 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
> register: %vreg7 +[496r,592B:0) +[880B,1088r:0)
> 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0,
> 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vr...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Thank for your help. You're right, merging vreg32 and vreg48 is perfectly fine, sorry I missed that.
I "brute force" debuged by adding MachineFunction dump after each join, I think I found the issue : it's when vreg32 and vreg10 are merged.
vreg10 only appears in BB#3, and the join only occurs in BB#3 apparently even if vreg32 lives in the 4 machine blocks
After joining, there
2012 Oct 25
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 25/10/2012 18:14, Vincent Lejeune wrote:
> When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg.
>
> If I look at the :
> %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
>
> instructions ; it gets joined to :
> 928B%vreg34<def> = COPY %vreg48:sel_y;
>
> when vreg6 and