Displaying 2 results from an estimated 2 matches for "6jgxqf1gcqaj".
2015 Sep 17
2
Register Number
On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:
> It seems like d0 is always 14!
> I check it with ARMGenAsmMatcher.inc it was the same!
> How is it possible? because it should give the same register value that
> matches the underlying platform not any autogenerated value!?
The returned number is the register id as defined in
<YourTarget>GenRegisterInfo.inc. These numbers
2015 Sep 17
2
Register Number
On 9/17/2015 8:30 AM, Sky Flyer wrote:
> Hi Krzysztof,
>
> Thanks for your reply. I wanted to assign the hardware encoding to the
> Instruction bits like the link below:
>
> https://groups.google.com/d/msg/llvm-dev/BfUmfIWYRM8/6JGXQf1gCQAJ
>
> but, at the end, what is assigned to the Inst is, I suppose, the
> register ID not the encoding!
>
> to be more clear, I do the followings:
> *def D0 : TestReg<0x01, "d0">, DwarfRegNum<[0]>;*
>
> and then in InstInfo.td
> *bits<6> Dr;
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