Displaying 2 results from an estimated 2 matches for "6f66bd03f829".
2015 Sep 03
3
[PATCH 0/3] New instmem implementation for Tegra
Due to the lack of implicit synchronization between CPU and GPU on Tegra systems
(like what PCI provides for dGPUs), the instmem implementation of GK20A/GM20B
relied on the slow, legacy PRAMIN so that CPU accesses used the same path as
GPU, making sure we see the same data on both ends.
The recent Nouveau refactoring introduced acquire/release functions on instmem
that help us understand the
2015 Sep 03
2
[PATCH 2/3] ltc/gf100: add flush/invalidate functions
...gm107_ltc_zbc_clear_color,
> .zbc_clear_depth = gm107_ltc_zbc_clear_depth,
> + .invalidate = gf100_ltc_invalidate,
> + .flush = gf100_ltc_flush,
> };
>
> int
> diff --git a/drm/nouveau/nvkm/subdev/ltc/priv.h b/drm/nouveau/nvkm/subdev/ltc/priv.h
> index 6f66bd03f829..4e3755b82769 100644
> --- a/drm/nouveau/nvkm/subdev/ltc/priv.h
> +++ b/drm/nouveau/nvkm/subdev/ltc/priv.h
> @@ -29,4 +29,6 @@ void gf100_ltc_cbc_clear(struct nvkm_ltc *, u32, u32);
> void gf100_ltc_cbc_wait(struct nvkm_ltc *);
> void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, in...