Displaying 3 results from an estimated 3 matches for "6f2".
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62
2007 May 29
2
interrupt loading, intrd, and CMT
...I want to be sure that this is the design, and
not just a coincidence of the current implementations.
Here''s the output from the x86 machines I could find:
psrinfo -vp on a single socket Intel Core 2 Duo system:
The physical processor has 2 virtual processors (0 1)
x86 (GenuineIntel 6F2 family 6 model 15 step 2 clock 1800 MHz)
Intel(r) Core(tm)2 CPU 4300 @ 1.80GHz
psrinfo -vp on an x4200:
The physical processor has 2 virtual processors (0 1)
x86 (AuthenticAMD 20F12 family 15 model 33 step 2 clock 2393 MHz)
Dual Core AMD Opteron(tm) Processor 280
The p...
2007 Apr 30
0
[LLVMdev] Boostrap Failure -- Expected Differences?
...72 je 762 <__FUNCTION__.22568+0x7a>
> - 6f0: 75 65 jne 757 <__FUNCTION__.22568+0x6f>
> + 6ee: 74 72 je 762 <__FUNCTION__.22481+0x7a>
> + 6f0: 75 65 jne 757 <__FUNCTION__.22481+0x6f>
> 6f2: 5f pop %edi
> 6f3: 64 fs
> 6f4: 65 gs
> - 6f5: 70 65 jo 75c <__FUNCTION__.22568+0x74>
> + 6f5: 70 65 jo 75c <__FUNCTION__.22481+0x74>
> 6f7: 6e ou...
2007 Apr 27
2
[LLVMdev] Boostrap Failure -- Expected Differences?
The saga continues.
I've been tracking the interface changes and merging them with
the refactoring work I'm doing. I got as far as building stage3
of llvm-gcc but the object files from stage2 and stage3 differ:
warning: ./cc1-checksum.o differs
warning: ./cc1plus-checksum.o differs
(Are the above two ok?)
The list below is clearly bad. I think it's every object file in
the