Displaying 2 results from an estimated 2 matches for "6aa9c7fe".
2018 Jul 25
2
Question about target instruction optimization
This is a question about optimizing the code generation in a (new) Z80
backend:
The CPU has a couple of 8 bit physical registers, e.g. H, L, D and E,
which are overlaid in 16 bit register pairs named HL and DE.
It has also a native instruction to load a 16 bit immediate value into a
16 bit register pair (HL or DE), e.g.:
LD HL,<imm16>
Now when having a sequence of loading two 16
2018 Jul 25
2
Question about target instruction optimization
...>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
> <http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20180726/6aa9c7fe/attachment.html>