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I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts...

I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the high and low parts of an SDValue. On 10 Nov 2013, at 17:50, Steve Montgomery <stephen.montgomery3 at btinternet.com> wrote: > I had a similar problem with a backend for the 68HC12 family which also has no barrel shifter. Some 68HC12 CPUs support shift for just one of the 16-bit registers and only support rotation on the 2 8-bit subregs of that 16-bit register. That means the only practical solution for 32-bit shifts is to lower to a libcall but my situation for 16-bit shifts...

Dear All, I am trying to custom lower 32-bit ISD::SHL and SHR in a backend for 6502 family CPUs. The particular subtarget has 16-bit registers at most, so a 32-bit result is not legal. Normally, if you mark this as "Legal" or "Expand", then it will expand the node into a more nodes as follows in an example: shl i32 %a , 2 => high_sdvalue = (or (shr %b, 14), (shl %c, 2) )

...wrote: > I forgot to mention that I used EXTRACT_ELEMENT in my backend to get the > high and low parts of an SDValue. > > On 10 Nov 2013, at 17:50, Steve Montgomery < > stephen.montgomery3 at btinternet.com> wrote: > > > I had a similar problem with a backend for the 68HC12 family which also > has no barrel shifter. Some 68HC12 CPUs support shift for just one of the > 16-bit registers and only support rotation on the 2 8-bit subregs of that > 16-bit register. That means the only practical solution for 32-bit shifts > is to lower to a libcall but my situati...