search for: 688r

...es two COPYs back to sibling value after the loop. My apologies [vregs 76->111, 87->122]. 1. The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense. selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02 ... queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r queuing new interval: %vreg122 [68...

...ter the loop. My apologies [vregs 76->111, 87->122]. >> >> 1. >> The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense. >> selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02 >> … >> queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r >> queuing n...

Hi Quentin, I have tried to find a test case for an official target, but failed. It seems to be a rare case. To do it, I added the 'else' clause in the following: ... if (VNI->def == OrigVNI->def) { DEBUG(dbgs() << "orig phi value\n"); SVI->second.DefByOrigPHI = true; SVI->second.AllDefsAreReloads = false; propagateSiblingValue(SVI); continue;

...2:%vreg39 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 R600_Reg128:%vreg6 register: %vreg40 +[640r,656r:0) 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 R600_Reg128:%vreg6 register: %vreg41 +[672r,688r:0) 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 R600_Reg128:%vreg6 register: %vreg42 +[704r,720r:0) 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 736B%vreg43<def> = COPY %vr...

...= COPY %vreg6:sel_y; R600_Reg32:%vreg40 > R600_Reg128:%vreg6 > register: %vreg40 +[640r,656r:0) > 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 > 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 > R600_Reg128:%vreg6 > register: %vreg41 +[672r,688r:0) > 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 > 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 > R600_Reg128:%vreg6 > register: %vreg42 +[704r,720r:0) > 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 > 73...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2