search for: 672r

...ging turned on: $llc bugpoint.reduced.simplified.bc -debug ... 208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34 Considering merging to VecRegs with %vreg34 in %vreg13 RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r LHS = %vreg13 [96r,112r:0)[112r,208r...

..._Reg32:%vreg39 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 R600_Reg128:%vreg6 register: %vreg40 +[640r,656r:0) 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 R600_Reg128:%vreg6 register: %vreg41 +[672r,688r:0) 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 R600_Reg128:%vreg6 register: %vreg42 +[704r,720r:0) 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 736B%vreg43<def> = COP...

...f> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 > R600_Reg128:%vreg6 > register: %vreg40 +[640r,656r:0) > 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 > 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 > R600_Reg128:%vreg6 > register: %vreg41 +[672r,688r:0) > 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 > 704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42 > R600_Reg128:%vreg6 > register: %vreg42 +[704r,720r:0) > 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 &g...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2