Displaying 3 results from an estimated 3 matches for "66f36e91".
2007 Feb 10
0
[LLVMdev] variant generation question
On Fri, 9 Feb 2007, Scott Michel wrote:
> I would have expected four additional patterns, each with the (and $rC, $rA)
> variant in it. But I only get the above four.
>
> Is this a bug or a feature? :-)
This is a feature. They would match the same pattern, so it would just be
generating dead code. For the same reason, if you write something like:
(set $rd, (and $rs, 123))
you
2007 Feb 13
1
[LLVMdev] variant generation question
...rB, (not $rC)))
(or (and $rC, $rA), (and (not $rC), $rB))
(or (and $rB, (not $rC)), (and $rC, $rA))
(or (and (not $rC), $rB), (and $rC, $rA))
-scooter
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070213/66f36e91/attachment.html>
2007 Feb 10
2
[LLVMdev] variant generation question
I've got an instruction that has the following pattern (R32C is the
32-bit register class):
(set R32C:$rT, (or (and R32C:$rA, R32C:$rC),
(and R32C:$rB, (not R32C:$rC))))
tblgen generates the following variants (I've dropped the R32C for
brevity):
(or (and $rA, $rC), (and $rB, (not $rC))) # original
(or (and $rA, $rC), (and (not $rC), $rB))
(or (and $rB, (not