search for: 65

...0 2 3 0 0 4 0 0 0 f2 2 0 0 8 0 0 0 1 0 0 0 fa 2 0 0 b0 0 0 0 96 3 0 0 c 0 0 0 4 0 0 0 a2 3 0 0 4 0 0 0 92 3 0 0 18 0 0 0 1 0 0 0 aa 3 0 0 10 0 0 0 a6 3 0 0 16 0 0 0 1 0 0 0 bc 3 0 0 1e 0 0 0 c6 3 0 0 20 0 0 0 1 0 0 0 e6 3 0 0 1e 0 0 0 f0 3 0 0 10 0 0 0 1 0 0 0 0 4 0 0 32 0 0 0 6f 0 62 0 6a 0 65 0 63 0 74 0 47 0 55 0 49 0 44 0 0 0 f8 b3 f c6 9b 5e b9 43 ac 2d c7 db 67 5c 32 f3 64 0 65 0 73 0 63 0 72 0 69 0 70 0 74 0 69 0 6f 0 6e 0 0 0 0 0 0 0 64 0 72 0 69 0 76 0 65 0 72 0 4e 0 61 0 6d 0 65 0 0 0 48 0 50 0 20 0 4c 0 61 0 73 0 65 0 72 0 4a 0 65 0 74 0 20 0 32 0 33 0 30 0 30 0 20 0 53...

...onfigure and make depend go fine. During the make, I get the following error... gcc -c -I. -I. -I../../include -I../../include -g -O2 -Wall -mpreferred-stack-boundary=2 -fPIC -D__WINE__ -D_REENTRANT -I/usr/X11R6/include -o ddraw/hal.o ddraw/hal.c In file included from ddraw/hal.c:20: ddraw/gl.h:65: parse error before `PFNGLACTIVETEXTUREARBPROC' ddraw/gl.h:65: warning: no semicolon at end of struct or union ddraw/gl.h:65: warning: type defaults to `int' in declaration of `glClientActiveTextureARB' ddraw/gl.h:65: warning: data definition has no type or storage class ddraw/gl.h:65:...

...45 [0] 046 [0] 047 [ 0.176001] pcpu-alloc: [0] 048 [0] 049 [0] 050 [0] 051 [ 0.176003] pcpu-alloc: [0] 052 [0] 053 [0] 054 [0] 055 [ 0.176004] pcpu-alloc: [0] 056 [0] 057 [0] 058 [0] 059 [ 0.176005] pcpu-alloc: [0] 060 [0] 061 [0] 062 [0] 063 [ 0.176006] pcpu-alloc: [0] 064 [0] 065 [0] 066 [0] 067 [ 0.176007] pcpu-alloc: [0] 068 [0] 069 [0] 070 [0] 071 [ 0.176008] pcpu-alloc: [0] 072 [0] 073 [0] 074 [0] 075 [ 0.176010] pcpu-alloc: [0] 076 [0] 077 [0] 078 [0] 079 [ 0.176011] pcpu-alloc: [0] 080 [0] 081 [0] 082 [0] 083 [ 0.176012] pcpu-alloc: [0] 084 [0] 085...

...ahmed" <hahmed2305 at gmail.com > <mailto:hahmed2305 at gmail.com>> wrote: > > Hello, > i am experimenting with the increase in register/ vector width to > 64 elements of 32 bits instead of 16 in x86 backend. > for eg. > i have a loop with 65 iterations; > if my IR generates v64i32 and 1 scalar, still the backend breaks > the v64i32 into 4 v16i32. i want it to retain v64i32. like if > there are 128 elements in loop then it should break it into 2 > v64i32 instructions. > > in order to do this i have...

...90:3c:00:a1:01:0a:d7:90:3c:00:a2:01:0a:d7:90:3c:00:a4:01:0a:d7:90:3c:00:a5:01:0a:d7:90:3c:00:a6:01:0a:d7:90:3c:00:a7:01:0a:d7:90:3c:00:a8:01:0a:d7:90:3c:00:a9:01:0a:d7:90:3c:00:aa:01:0a:d7:90:3c:00:ab:01:0a:d7:90:3c:00:ac:01:0a:d7:90:3c:00:83:01:0a:d7:90:3c:bb:bb:01:0a:d7:90:3c:ff:09:cb:00:00:16:4e:65:78:74:20:44:65:76:69:63:65:20:28:42:49:4f:53:2f:45:46:49:29:00:a0:0c:55:62:75:6e:74:75:4e:65:74:78:38:36:00:81:08:44:4f:53:20:55:4e:44:49:00:a1:0c:48:50:20:64:63:37:38:30:30:53:46:46:00:a2:0b:44:65:6c:6c:20:4f:70:74:33:36:30:00:a4:0b:47:58:35:32:30:26:47:58:36:32:30:00:a5:16:42:72:6f:61:64:4e:65:74...

...gt; On Jul 6, 2017 5:18 PM, "hameeza ahmed" <hahmed2305 at gmail.com> wrote: >> >> Hello, >> i am experimenting with the increase in register/ vector width to 64 >> elements of 32 bits instead of 16 in x86 backend. >> for eg. >> i have a loop with 65 iterations; >> if my IR generates v64i32 and 1 scalar, still the backend breaks the >> v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 >> elements in loop then it should break it into 2 v64i32 instructions. >> >> in order to do this i have made...

...;m using deSolve. Here is my code so far. library(deSolve); Izhikevich <- function(time, init, parms) { with(as.list(c(init, parms)),{ dv <- (0.04*v^2)+(5*v)+140-u+I; du <- a*(b*v-u); if (v>=30) v<-c else v<-u+d; list( c(dv, du)) })} parms=c( a=0.02, b=0.2, c=-65, d=8,I=10); times=seq(from=1, to=1000, by=1); init=c(v=-65, u=0.2); out<-ode(y=init, times=times, func=Izhikevich, parms=parms) plot(out) Can someone perhaps help me out? Regards Jannetta -- =================================== Web site: http://www.jannetta.com Email: jannetta@henning.org =...

On Fri, Feb 07, 2020 at 08:47:14AM +0100, Christian Borntraeger wrote: > Also adding Cornelia. > > > On 06.02.20 23:17, Michael S. Tsirkin wrote: > > On Thu, Feb 06, 2020 at 04:12:21PM +0100, Christian Borntraeger wrote: > >> > >> > >> On 06.02.20 15:22, eperezma at redhat.com wrote: > >>> Hi Christian. > >>> > >>>

On Fri, Feb 07, 2020 at 08:47:14AM +0100, Christian Borntraeger wrote: > Also adding Cornelia. > > > On 06.02.20 23:17, Michael S. Tsirkin wrote: > > On Thu, Feb 06, 2020 at 04:12:21PM +0100, Christian Borntraeger wrote: > >> > >> > >> On 06.02.20 15:22, eperezma at redhat.com wrote: > >>> Hi Christian. > >>> > >>>

..., with seemingly the same condition, don't work, even on the same W2K client machines. I'v turned debugging up to 10 and I'm getting a better view of the issue. It seems to have something to do with a file path not being found. The applicaiton error message is [000] 01 BD 0F 20 52 65 71 75 69 72 65 64 20 70 72 6F ... Requ ired pro [2001/03/16 03:38:06, 10] lib/util.c:dump_data(2926) [010] 70 65 72 74 79 20 66 6F 72 20 74 68 69 73 20 66 perty fo r this f [2001/03/16 03:38:06, 10] lib/util.c:dump_data(2926) [020] 69 65 6C 64 20 69 73 20 73 65 74 20 74 6F 20 54 ield is...

...39c: R_386_32 gt_ggc_mx_varray_head_tag > 3a0: R_386_32 gt_pch_nx_varray_head_tag > > -000003b8 <__FUNCTION__.20147>: > +000003b8 <__FUNCTION__.20062>: > 3b8: 66 69 6e 64 5f 62 imul $0x625f,0x64(%esi),%bp > 3be: 61 popa > - 3bf: 73 65 jae 426 <__FUNCTION__.20952+0xa> > + 3bf: 73 65 jae 426 <__FUNCTION__.20866+0xa> > 3c1: 5f pop %edi > 3c2: 64 65 63 6c 00 2f arpl %bp,%fs:%gs:0x2f(%eax,%eax,1) > > 000003c7 <.str>: > 3c7: 2f...

...ge), the year of registration (reg) and a measure of the policyholders claim history called the no claim discount (ncd). Define p(i,j,k) as the probability of a policyholder in level i of age, level j of reg and level k of ncd making a claim (for i= 1 (age= 17-22), 2 (23-26), 3 (27-65), 4 (66-80) ; j=1 (registration after 1964), 2 (63-64), 3 (60-62), 4 (earlier than 1960) and ncd= 1 (1-1 claims), 2 (2-3), 3 (more than three).). Similarly define r(i,j,k) as the proportion of policyholders in level i of age, level j of reg and level k of ncd making a claim. We ca...

...56 69 .100 SIP /2.0..Vi 0050 61 3a 20 53 49 50 2f 32 2e 30 2f 55 44 50 20 31 a: SIP/2 .0/UDP 1 0060 39 32 2e 31 36 38 2e 31 2e 31 31 36 3a 35 34 30 92.168.1 .116:540 0070 35 30 3b 62 72 61 6e 63 68 3d 7a 39 68 47 34 62 50;branc h=z9hG4b 0080 4b 2d 64 38 37 35 34 7a 2d 32 34 32 38 38 65 37 K-d8754z -24288e7 0090 32 38 32 36 64 30 31 32 38 2d 31 2d 2d 2d 64 38 2826d012 8-1---d8 00a0 37 35 34 7a 2d 3b 72 70 6f 72 74 0d 0a 4d 61 78 754z-;rp ort..Max 00b0 2d 46 6f 72 77 61 72 64 73 3a 20 37 30 0d 0a 43 -Forward s: 70..C 00c0 6f 6e 74 61 63 74 3a 20 3c 73 69 70 3a 31 32...

Dear R users, I have received a table in the following format: id a b c1 c2 d1 d2 1 1 1 65 97 78 98 2 1 2 65 97 42 97 3 2 1 65 68 97 98 4 2 2 65 97 97 98 Factors of the design are: a, b, and e, where e has levels c and d. The levels c and d then have 2 replicates (r) each. Now I would like to get: id a b e r value 1 1 1 c 1 65 2 1 1 c...

...0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 [953] 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 [1009] 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 [1065] 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 [1121] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0 0 0 [1177] 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0...

Hello, i am experimenting with the increase in register/ vector width to 64 elements of 32 bits instead of 16 in x86 backend. for eg. i have a loop with 65 iterations; if my IR generates v64i32 and 1 scalar, still the backend breaks the v64i32 into 4 v16i32. i want it to retain v64i32. like if there are 128 elements in loop then it should break it into 2 v64i32 instructions. in order to do this i have made necessary changes in X86ISelLowering.cpp. an...

[Re-directing to R-help, as this is more appropriate there.] I tried copying the snippet of data into the windows clipboard and tried it: > dat <- read.table("clipboard", header=T) > dat Name Weight Height Gender 1 Anne 150 65 F 2 Rob 160 68 M 3 George 180 65 M 4 Greg 205 69 M > str(dat) `data.frame': 4 obs. of 4 variables: $ Name : Factor w/ 4 levels "Anne","George",..: 1 4 2 3 $ Weight: int 150 160 180 205 $ Height: int 65 68 65 69 $ Gen...

The saga continues. I've been tracking the interface changes and merging them with the refactoring work I'm doing. I got as far as building stage3 of llvm-gcc but the object files from stage2 and stage3 differ: warning: ./cc1-checksum.o differs warning: ./cc1plus-checksum.o differs (Are the above two ok?) The list below is clearly bad. I think it's every object file in the

.... I am trying to construct a frequency table. I guess this should be done with table. Or perhaps factor and split. Or prop.table. cut? findInterval? Argh! Please correct me if what I am looking for is not called a "frequency table". Perhaps it's called grouped data. > zz$x9 [1] 65 70 85 65 65 65 62 55 82 59 55 66 74 55 65 56 80 73 45 64 75 58 60 56 60 [26] 65 53 63 72 80 90 95 55 70 79 62 57 65 60 47 61 53 80 75 72 87 52 72 80 85 [51] 75 70 84 60 72 70 76 70 79 72 69 80 62 74 54 58 58 69 81 84 I (think) I want it to look like: 40-49 2 50-59 15 60-69 20 70-79 19 80-...

...g chars 0x60 0x0 (l->u = False) (u->l = False) Adding chars 0x61 0x0 (l->u = False) (u->l = False) Adding chars 0x62 0x0 (l->u = False) (u->l = False) Adding chars 0x63 0x0 (l->u = False) (u->l = False) Adding chars 0x64 0x0 (l->u = False) (u->l = False) Adding chars 0x65 0x0 (l->u = False) (u->l = False) Adding chars 0x66 0x0 (l->u = False) (u->l = False) Adding chars 0x67 0x0 (l->u = False) (u->l = False) Adding chars 0x68 0x0 (l->u = False) (u->l = False) Adding chars 0x69 0x0 (l->u = False) (u->l = False) Adding chars 0x6a 0x0 (l-&g...