search for: 64xi32

...he problem >>> that i have mentioned. actually i am doing all the things step by step. >>> >>> so i havent yet worked with instruction selection phase/ files. rather >>> before that i am trying to do legalization by allowing vector elements>16 >>> i.e 64xi32. here i have mainly worked with 2 files uptil now, i.e >>> registerinfo.td to define register class to be called in legalization. >>> and most importantly i am dealing with file X86ISelLowering.cpp. >>> >>> Now is there any relation in this and instruction select...

...n in the square bracket to match an add node. You > also need two VR2048 registers in the 'ins' > > ~Craig > > On Fri, Jul 7, 2017 at 9:29 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> Can you please tell whether following add is correct to add 2 64xi32 >> numbers. >> >> def VADD_256B : RI<0xFE, MRMDestReg, (outs VR2048:$dst), (ins VR2048 >> :$src), >> "VADD_256B\t{$src, $dst|$dst, $src}", [], >> IIC_XADD_REG>, TB; >> >> what is llc_xadd_reg here? >> >>...

...eza ahmed < >>>>>>>>>>> hahmed2305 at gmail.com> wrote: >>>>>>>>>>> >>>>>>>>>>>> Can you please tell whether following add is correct to add 2 >>>>>>>>>>>> 64xi32 numbers. >>>>>>>>>>>> >>>>>>>>>>>> def VADD_256B : RI<0xFE, MRMDestReg, (outs VR2048:$dst), (ins >>>>>>>>>>>> VR2048:$src), >>>>>>>>>>>>...

...ly i am doing all the things step by >>>>> step. >>>>> >>>>> so i havent yet worked with instruction selection phase/ files. rather >>>>> before that i am trying to do legalization by allowing vector elements>16 >>>>> i.e 64xi32. here i have mainly worked with 2 files uptil now, i.e >>>>> registerinfo.td to define register class to be called in >>>>> legalization. and most importantly i am dealing with file >>>>> X86ISelLowering.cpp. >>>>> >>>>> Now...

...seen these links. but they dont cover the problem > that i have mentioned. actually i am doing all the things step by step. > > so i havent yet worked with instruction selection phase/ files. rather > before that i am trying to do legalization by allowing vector elements>16 > i.e 64xi32. here i have mainly worked with 2 files uptil now, i.e > registerinfo.td to define register class to be called in legalization. > and most importantly i am dealing with file X86ISelLowering.cpp. > > Now is there any relation in this and instruction selection. since > instruction sele...

Have you read http://llvm.org/docs/WritingAnLLVMBackend.html and http://llvm.org/docs/CodeGenerator.html ? http://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector describes how to define a store instruction. -Eli On 7/6/2017 6:51 PM, hameeza ahmed via llvm-dev wrote: > Please correct me i m stuck at this point. > > On Jul 6, 2017 5:18 PM, "hameeza ahmed"