search for: 640r

...ppening is that although execution reaches to the line spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r >From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 640e %R15R14<def> = COPY %vreg28<kill>...

On Nov 30, 2011, at 12:17 PM, Borja Ferrer wrote: > Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): > > for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if

...that although execution reaches to the line spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: > > Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r > From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r > Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 > remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 > 640e %R15R14<def> = COPY %vr...

Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg)

...derived from  608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 R600_Reg128:%vreg6 register: %vreg39 +[608r,624r:0) 624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 R600_Reg128:%vreg6 register: %vreg40 +[640r,656r:0) 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 R600_Reg128:%vreg6 register: %vreg41 +[672r,688r:0) 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 704B%vreg42<def> = COPY %vreg6:sel...

...f> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 > R600_Reg128:%vreg6 > register: %vreg39 +[608r,624r:0) > 624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39 > 640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 > R600_Reg128:%vreg6 > register: %vreg40 +[640r,656r:0) > 656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40 > 672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 > R600_Reg128:%vreg6 > register: %vreg41 +[672r,688r:0) > 688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41 > 704B%vreg...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2