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...do at this point. Should we integrate our work (an alternate register pressure reduction scheduler) into the SD scheduler or the MI scheduler? Please refer to my recent messages on llvmdev regarding enabling MI scheduling by default on x86. http://article.gmane.org/gmane.comp.compilers.llvm.devel/63242/match=machinescheduler I suggest integrating with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse Sched...

...this point. Should we integrate our work (an alternate register pressure reduction scheduler) into the SD scheduler or the MI scheduler? > Please refer to my recent messages on llvmdev regarding enabling MI scheduling by default on x86.  http://article.gmane.org/gmane.comp.compilers.llvm.devel/63242/match=machinescheduler I suggest integrating with the MachineScheduler pass. There are many places to plug in. MachineSchedRegistry provides the hook. At that point you can define your own ScheduleDAGInstrs or ScheduleDAGMI subclass. People who only want to define new heuristics should reuse Sched...

Hi, I'm interested in the two pre-RA instruction schedulers used in LLVM, list-hybrid and list-ilp. I've done some digging on the internet and played around with executing some test files using the two schedules. However, I'm still uncertain of the behaviors and heuristics used in each. For example, the XXXX_ls_rr_sort::isReady for hybrid includes a 3 cycle readydelay (seems

...age mean? > Is this a bug or we are doing something wrong? I’m not sure why the driver is telling you this. Maybe someone familiar with dragonegg can help? You can always rebuild llvm with the enableMachineScheduler() hook implemented. http://article.gmane.org/gmane.comp.compilers.llvm.devel/63242/match=machinescheduler Then -enable-misched=true/false simply toggles MI Sched without changing anything else. > How can we test the MI scheduler by itself? > Is it interesting to test 3.3 or there are interesting features that were added to the trunk after branching 3.3? In the latter cas...

Hi, We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine instruction (MI) scheduler has been implemented to replace (or work with?) the selection DAG (SD) scheduler. However, I could not find any document that