search for: 5zeudvxk

Thanks for the suggestion. I ran verify-machineinstrs and found that I've definitely been doing something wrong, for quite a while at least (I assume that live interval analysis and the particular benchmark just happened to expose it). Results are at http://pastebin.com/5zeUDVXK. I'm not entirely sure what is wrong here - I assume it has something to do with my 'special' instruction LDri_ab. This instruction is a load with an 'address writeback' - ld.ab r0, [r1, 5] is equivalent to ld r0, [r1]; add r1, r1, 5. As it was very difficult to match such beha...

I have a target backend which is currently causing live interval analysis to throw 'Interval not live at use' errors for many of my benchmarks. I imagine that this is caused by missing information for my target (probably in the instructioninfo tablegen?), but I am having difficulties in both debugging and fixing this problem, and would appreciate any advice or help anyone can give.