Displaying 3 results from an estimated 3 matches for "5c00ae0a".
2012 Sep 10
0
[LLVMdev] Assert in LiveInterval update
On Sep 10, 2012, at 2:26 AM, Lang Hames <lhames at gmail.com> wrote:
> I've got a good test case that I'm working on at the moment. I noticed something odd though: Is '0' a valid register unit? I'm seeing a LiveInterval with li->reg == 0 show up, which previously wasn't valid. We have a few checks around the place to disregard the '0' physreg - could
2012 Sep 12
1
[LLVMdev] Assert in LiveInterval update
...ecause the set of super-registers can be quite large on ARM.
>
Done. I've used TRI.hasRegUnit as suggested. Thanks for the advice!
Cheers,
Lang.
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2012 Sep 10
3
[LLVMdev] Assert in LiveInterval update
Hi Jakob,
I've got a good test case that I'm working on at the moment. I noticed
something odd though: Is '0' a valid register unit? I'm seeing a
LiveInterval with li->reg == 0 show up, which previously wasn't valid. We
have a few checks around the place to disregard the '0' physreg - could
these trigger on interaction with a '0' interval? That could