search for: 59c155a7

Displaying 2 results from an estimated 2 matches for "59c155a7".

2011 May 16
0
[LLVMdev] TargetRegisterInfo and "infinite" register files
Justin, We have the same issue with the AMDIL code generator. We tried #1, but there are passes after register allocator that don't like virtual registers. #3 could be done by having the two spill functions [load|store]Reg[From|To]StackSlot keep track of the FrameIndex to register mapping internally, but again, more of a hack than a proper solution. My solution was to just create a very large
2011 May 16
6
[LLVMdev] TargetRegisterInfo and "infinite" register files
Currently, the TableGen register info files for all of the back-ends define concrete registers and divide them into logical register classes. I would like to get some input from the LLVM experts around here on how best to map this model to an architecture that does *not* have a concrete, pre-defined register file. The architecture is PTX, which is more of an intermediate form than a final