search for: 576b

...RegAliasIterator to dynamically compute the register aliases. The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation seems to imply this is a safe assumption and I haven't found a client that requires these attributes...

LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also

...reg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 560BJUMP <BB#3>, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg // LOOP BODY 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R60...

...7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 > 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 > 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 > 560BJUMP <BB#3>, pred:%PREDICATE_BIT > 576BJUMP <BB#2>, pred:%noreg > > // LOOP BODY > 896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6 > 912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32 R600_Reg32:%vreg31 > 928B%vreg34<def> = COPY %vreg6:sel_y...