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572acd24
2013 Nov 15
0
[LLVMdev] Limit loop vectorizer to SSE
Hmm.. I don't quite understand. How can a module validator
catch this, when it's the pointers, i.e. the payload, you pass
as function arguments that need to be aligned.. ?!
Frank
On 15/11/13 15:16, Renato Golin wrote:
> On 15 November 2013 20:05, Frank Winter <fwinter at jlab.org
> <mailto:fwinter at jlab.org>> wrote:
>
> Good catch! That was the problem in my
2013 Nov 15
3
[LLVMdev] Limit loop vectorizer to SSE
On 15 November 2013 20:05, Frank Winter <fwinter at jlab.org> wrote:
> Good catch! That was the problem in my case too. I totally
> overlooked the alignment requirement for AVX.
I wonder if the validation mechanism shouldn't have caught it earlier... Do
you guys run validate on the modules before JIT-ing?
--renato
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2013 Nov 15
2
[LLVMdev] Limit loop vectorizer to SSE
...on mechanism shouldn't have caught it earlier...
> Do you guys run validate on the modules before JIT-ing?
>
> --renato
>
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