search for: 544r

...) +[880B,1088r:0) 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 register: %vreg29 +[512r,528r:0) 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 register: %vreg30 +[528r,544r:0) 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30 560BJUMP <BB#3>, pred:%PREDICATE_BIT 576BJUMP <BB#2>, pred:%noreg BB#2:# derived from  608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 R600_Reg128:%vreg6 register: %vreg39 +[608r,62...

...B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, > 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 > register: %vreg29 +[512r,528r:0) > 528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29 > register: %vreg30 +[528r,544r:0) > 544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; > R600_Reg32:%vreg30 > 560BJUMP <BB#3>, pred:%PREDICATE_BIT > 576BJUMP <BB#2>, pred:%noreg > BB#2:# derived from  > 608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 > R600_Reg1...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2