Displaying 2 results from an estimated 2 matches for "542d6930".
2008 Oct 25
0
[LLVMdev] SetCC tablegen pattern
That's how ISD::SETCC is specified. If you want to change that for
your target, you should custom lower these nodes to target nodes. Then
you can specify your own SDNode with your own SDTypeProfile.
Evan
On Oct 24, 2008, at 4:31 PM, Villmow, Micah wrote:
> I am attempting to match setcc using tablegen w/ the following
> patterns:
> def FEQ : Instruction<(outs
2008 Oct 24
2
[LLVMdev] SetCC tablegen pattern
I am attempting to match setcc using tablegen w/ the following
patterns:
def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0,
GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq
GPRF32:$src0, GPRF32:$src1))]>;
And it is failing stating that the result must be an integer. Is there a
way around this other than modifying TargetSelectionDAG.td? Also,