Displaying 1 result from an estimated 1 matches for "52f51831".
2016 Oct 17
4
LLVM backend -- Avoid base+index address mode for X86
Hi All,
I have a question regarding LLVM backend. I appreciate a lot if anyone can
provide some hints.
My work here is to avoid base+index address mode for X86 target, to allow
base-register only or index-register only address mode. For example,
"mov (%rsi), %rbx" is allowed, but "mov (%rsi, %rax), %rbx" is not allowed.
I understand LLVM backend is a complex system. Can any