search for: 52aa30f2524d

Displaying 3 results from an estimated 3 matches for "52aa30f2524d".

2020 Feb 13
1
[PATCH 1/4] drm/nouveau/kms/nv50-: Probe SOR caps for DP interlacing support
...led to apply! Possible dependencies: 11fc017dfb1e ("drm/nouveau/kms/nv50: prepare for double-buffered LUTs") 34508f9d260c ("drm/nouveau/kms/nv50-: determine MST support from DP Info Table") 3dbd036b8419 ("drm/nouveau/kms/nv50: separate out mode commit") 52aa30f2524d ("drm/nouveau/kms/nv50: switch mst sink back into sst mode") 698c1aa9f83b ("drm/nouveau/kms/nv50-: Don't create MSTMs for eDP connectors") 6bbab3b6b656 ("drm/nouveau/kms/nv50: separate out base/ovly channel usage bounds commit") a7ae1561909d ("drm/...
2020 Feb 12
8
[PATCH 0/4] drm/nouveau: DP interlace fixes
Currently, nouveau doesn't actually bother to try probing whether or not it can actually handle interlaced modes over DisplayPort. As a result, on volta and later we'll end up trying to set an interlaced mode even when it's not supported and cause the front end for the display engine to hang. So, let's teach nouveau to reject interlaced modes on hardware that can't actually
2019 Sep 13
6
[PATCH 1/4] drm/nouveau: dispnv50: Don't create MSTMs for eDP connectors
On the ThinkPad P71, we have one eDP connector exposed along with 5 DP connectors, resulting in a total of 11 TMDS encoders. Since the GPU on this system is also capable of MST, we create an additional 4 fake MST encoders for each DP port. Unfortunately, we also do this for the eDP port as well, resulting in: 1 eDP port: +1 TMDS encoder +4 DPMST encoders 5 DP ports: +2 TMDS