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Hi Dmitry, ISPC does some instruction selection as part of vectorization (on ASTs!) by placing intrinsics for specific operations. The SEXT to i32 pattern was implemented because LLVM did not support vector-selects when this code was written. Can you submit a small SSE4 test case that demonstrates the problem? Select is the canonical form of this operations, and SEXT is usually more

...t's performance regression after one of your commits. >> > >> > Thanks. >> > >> > Dmitry. >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131021/5209cc70/attachment.html>

Nadav, You are absolutely right, it's ISPC workload. I've checked SSE4 and it's also severely affected. We use intrinsics only for conversion <N x i32> <=> i32, i.e. movmsk.ps. For the rest we use general LLVM instructions. And I actually would really like to stick this way. We rely on LLVM's ability to produce efficient code from general LLVM IR. Relying on

...#39;s performance regression after one of your commits. >> > >> > Thanks. >> > >> > Dmitry. >> > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.cs.uiuc.edu/pipermail/llvmdev/attachments/20131021/5209cc70/attachment-0001.html> ------------------------------ Message: 6 Date: Mon, 21 Oct 2013 14:58:55 -0500 From: Arnold Schwaighofer <aschwaighofer at apple.com> To: Renato Golin <renato.golin at linaro.org> Cc: LLVM Dev <llvmdev at cs.uiuc.edu> Subject: Re: [LLVMdev] First attemp...