Displaying 4 results from an estimated 4 matches for "518,16".
2007 Apr 18
0
[RFC, PATCH 13/24] i386 Vmi system header
...ot;movl %0,%%cr4": :"r" (x));
-#define stts() write_cr0(8 | read_cr0())
-
#endif /* __KERNEL__ */
-#define wbinvd() \
- __asm__ __volatile__ ("wbinvd": : :"memory");
-
static inline unsigned long get_limit(unsigned long segment)
{
unsigned long __limit;
@@ -518,16 +459,7 @@ struct alt_instr {
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
-/* interrupt control.. */
-#define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
-#define...
2007 Apr 18
0
[RFC, PATCH 13/24] i386 Vmi system header
...ot;movl %0,%%cr4": :"r" (x));
-#define stts() write_cr0(8 | read_cr0())
-
#endif /* __KERNEL__ */
-#define wbinvd() \
- __asm__ __volatile__ ("wbinvd": : :"memory");
-
static inline unsigned long get_limit(unsigned long segment)
{
unsigned long __limit;
@@ -518,16 +459,7 @@ struct alt_instr {
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
-/* interrupt control.. */
-#define local_save_flags(x) do { typecheck(unsigned long,x); __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */); } while (0)
-#define...
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by