Displaying 6 results from an estimated 6 matches for "5056b".
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2012 Jul 14
2
[LLVMdev] Issue with Machine Verifier and earlyclobber
...oad with displacement instruction of the form "load reg,
[reg_addr+<offs>]", where reg_addr and dest can't be the same register.
This caused the following verifier error:
*** Bad machine code: No live range at def ***
- function: f3
- basic block: entry 0x9d68664 (BB#0) [0B;5056B)
- instruction: 3688B %vreg96<earlyclobber,def> = LDDWRdPtrQ <fi#0>, 0;
mem:LD2[FixedStack0](align=1) DREGS:%vreg96
- operand 0: %vreg96<earlyclobber,def>
3688e is not live in [3688r,4480r:0) 0 at 3688r
*** Bad machine code: Early clobber def must be at an early-clobber slo...
2014 Aug 22
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...is point I have the following live ranges for vreg1954:
%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r
And vreg1954 is mentioned in these instructions:
5000B %vreg1954:hi16<def,read-undef> = mv_any16 32766
[...]
5048B mv_ar16_r16_rmod1 %vreg1954:hi16, %vreg1753
5056B %vreg1954:lo16<def> = mv_nimm6_ar16 0
5064B Store40FI %vreg1954, <fi#2>
[...]
5128B %vreg223<def> = COPY %vreg1954
[...]
5216B %vreg1178<def> = COPY %vreg1954
[...]
5348B %vreg1955<def> = COPY %vreg1954
Then it tries to rematerialize:
Value %vreg...
2012 Jul 14
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
...ion of the form "load reg, [reg_addr+<offs>]", where reg_addr and dest can't be the same register.
>
> This caused the following verifier error:
>
> *** Bad machine code: No live range at def ***
> - function: f3
> - basic block: entry 0x9d68664 (BB#0) [0B;5056B)
> - instruction: 3688B %vreg96<earlyclobber,def> = LDDWRdPtrQ <fi#0>, 0; mem:LD2[FixedStack0](align=1) DREGS:%vreg96
> - operand 0: %vreg96<earlyclobber,def>
> 3688e is not live in [3688r,4480r:0) 0 at 3688r
>
> *** Bad machine code: Early clobber def must b...
2012 Jul 14
2
[LLVMdev] Issue with Machine Verifier and earlyclobber
...gt; [reg_addr+<offs>]", where reg_addr and dest can't be the same register.
> >
> > This caused the following verifier error:
> >
> > *** Bad machine code: No live range at def ***
> > - function: f3
> > - basic block: entry 0x9d68664 (BB#0) [0B;5056B)
> > - instruction: 3688B %vreg96<earlyclobber,def> = LDDWRdPtrQ <fi#0>,
> 0; mem:LD2[FixedStack0](align=1) DREGS:%vreg96
> > - operand 0: %vreg96<earlyclobber,def>
> > 3688e is not live in [3688r,4480r:0) 0 at 3688r
> >
> > *** Bad machine c...
2014 Aug 19
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi Quentin,
On 08/15/14 19:01, Quentin Colombet wrote:
[...]
>> The question is: How should true subregister definitions be
>> expressed so that they do not interfere with each other? See the
>> detailed problem description below.
>
> We do have a limitation in our current liveness tracking for
> sub-register. Therefore, I am not sure that is possible.
>
>
2012 Jul 15
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
...t;]", where reg_addr and dest can't be the same register.
>> >
>> > This caused the following verifier error:
>> >
>> > *** Bad machine code: No live range at def ***
>> > - function: f3
>> > - basic block: entry 0x9d68664 (BB#0) [0B;5056B)
>> > - instruction: 3688B %vreg96<earlyclobber,def> = LDDWRdPtrQ <fi#0>,
>> 0; mem:LD2[FixedStack0](align=1) DREGS:%vreg96
>> > - operand 0: %vreg96<earlyclobber,def>
>> > 3688e is not live in [3688r,4480r:0) 0 at 3688r
>> >
>>...